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intel ? ixf1110 10-port gigabit ethernet media access controller datasheet the intel ? ixf1110 is a 10-port ethernet media access controller (mac) that supports ieee 802.3 1000 mbps applications. the device supports a system packet interface level 4 phase 2 (spi4-2) system interface to the network processor or asic, and implements an internal serializer/deserializer (serdes) to allow direct connection to optical modules. the integration of the serdes functionality reduces pcb real-estate and system-cost requirements. applications in general, the ixf1110 is appropriate for high-end switching applications where mac and serdes functions are not integrated into the system asic. product features high-end optical ethernet switches multi-service optical ethernet switches high-end ethernet lan/wan routers serdes interface with optical module connections for ethernet physical connectivity ? integrated termination ?i 2 c read/write capability system packet interface level 4 phase 2 (spi4-2) ? capable of data transfers from 10.24 gbps up to 12.8 gbps ? supports dynamic phase alignment ? integrated termination ten independent 1000 mbps full-duplex ethernet mac ports 32-bit cpu interface operating temperature range: min max 0 c +70 c rmon statistics jtag boundary scan compliant with ieee 802.3x standard for flow control jumbo frame support for 9.6 kb packets .18 cmos process technology supports ieee 802.3 fiber auto- negotiation, including forced mode sfp msa compatible internal 17.0 kb receive fifo and 4.5 kb transmit fifo per port independent enable/disable of any port detection of overly large packets error counters for dropped and errored packets crc calculation and error detection programmable options: ? filter packets with errors ? filter, broadcast, multicast, and unicast address packets ? automatically pad transmitted packets less than the minimum frame size 552-ceramic ball grid array (cbga) 1.8 v and 2.5 v operation power consumption: 490 mw per-port typical product ordering number (mm): hfixf1110cc.b2: 860817 document number: 250210 revision number: 008 revision date: august 10, 2004
2 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? ixf1110 mac may contain design defects or errors known as errata which may cause the product to deviate from published specifi cations. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct media, dialogic, dm3, etherexpress, etox, flashfile , i386, i486, i960, icomp, instantip, intel, intel centrino, intel logo, inte l386, intel486, intel740, inteldx2, inteldx4, intelsx2, intel cr eate & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel play, intel play l ogo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, intel xscale, iplink, itanium, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress, voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2004, intel corporation
contents datasheet 3 document number: 250210 revision number: 008 revision date: august 10, 2004 contents 1.0 introduction................................................................................................................ .......13 1.1 what you will find in this document................................................................. 13 1.2 related documents.............................................................................................14 2.0 general description......................................................................................................... .15 3.0 ball assignments and ball list tables ............................................................................. 17 3.1 ball list tables ....................................................................................................18 3.1.1 balls listed in alphanumeric order by signal name.............................. 18 3.1.2 balls listed in alphanumeric order by ball location.............................. 24 4.0 ball assignments and signal descriptions .......................................................................30 4.1 naming conventions ...........................................................................................30 4.1.1 signal name conventions...................................................................... 30 4.1.2 register address conventions...............................................................30 4.2 interface signal groups....................................................................................... 31 5.0 functional descriptions ....................................................................................................4 3 5.1 media access controller .....................................................................................43 5.1.1 general description................................................................................43 5.1.2 mac functions.......................................................................................43 5.1.2.1 padding of undersized frames on transmit ............................. 43 5.1.2.2 automatic crc generation ....................................................... 44 5.1.2.3 filtering of receive packets......................................................44 5.1.3 flow control ...........................................................................................46 5.1.3.1 802.3x flow control (full-duplex operation) ............................ 46 5.1.4 fiber operation .....................................................................................50 5.1.5 auto-negotiation .................................................................................... 51 5.1.5.1 determining if link is established in auto-negotiation mode ... 51 5.1.6 forced mode operation ........................................................................ 52 5.1.6.1 determining if link is established in forced mode ...................52 5.1.7 jumbo packet support ...........................................................................52 5.1.8 rmon statistics support .......................................................................53 5.1.8.1 rmon statistics ........................................................................53 5.1.8.2 conventions ..............................................................................55 5.1.8.3 additional statistics ...................................................................55 5.2 system packet interface level 4 phase 2...........................................................57 5.2.1 data path ...............................................................................................58 5.2.1.1 control words ...........................................................................59 5.2.1.2 eop abort .................................................................................61 5.2.1.3 dip4 ..........................................................................................62 5.2.2 start-up parameters ..............................................................................63 5.2.2.1 calendar_len......................................................................63 5.2.2.2 calendar_m ..........................................................................64 5.2.2.3 dip2_thr ...................................................................................64 5.2.2.4 loss_of_sync ...........................................................................64 5.2.2.5 data_max_t...........................................................................64 5.2.2.6 rep_t.......................................................................................64
contents 4 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.2.2.7 dip4_unlock ............................................................................ 64 5.2.2.8 dip4_lock................................................................................. 64 5.2.2.9 maxburst1 ................................................................................. 65 5.2.2.10maxburst2 ................................................................................. 65 5.2.3 dynamic phase alignment training sequence (data path de-skew).... 65 5.2.3.1 training at start-up....................................................................65 5.2.3.2 periodic training ....................................................................... 65 5.2.3.3 training in a practical implementation ...................................... 66 5.2.4 fifo status channel ............................................................................. 66 5.2.5 dc parameters ...................................................................................... 70 5.3 serdes interface ................................................................................................ 70 5.3.1 introduction ............................................................................................ 70 5.3.2 features ................................................................................................. 70 5.3.3 functional description............................................................................ 71 5.3.3.1 transmitter operational overview............................................. 71 5.3.3.2 transmitter programmable driver-power levels ...................... 71 5.3.3.3 receiver operational overview.................................................72 5.3.3.4 selective power-down .............................................................. 72 5.3.4 timing and electrical characteristics ..................................................... 72 5.4 optical module interface .................................................................................... 72 5.4.1 introduction ............................................................................................ 72 5.4.2 ixf1110 supported optical module interface signals. .......................... 72 5.4.3 functional descriptions .......................................................................... 73 5.4.3.1 high-speed serial interface ...................................................... 73 5.4.3.2 low-speed status signaling interface ...................................... 73 5.4.4 i 2 c module configuration interface ........................................................ 75 5.4.4.1 general description................................................................... 76 5.4.4.2 i 2 c protocol specifics................................................................ 78 5.4.4.3 port protocol operation............................................................. 78 5.4.4.4 clock and data transitions ....................................................... 78 5.4.4.5 ac timing characteristics......................................................... 82 5.5 led interface ...................................................................................................... 82 5.5.1 introduction ............................................................................................ 82 5.5.2 modes of operation................................................................................ 82 5.5.2.1 mode 0 ...................................................................................... 83 5.5.2.2 mode 1 ...................................................................................... 83 5.5.3 led interface signal description ........................................................... 83 5.5.4 mode 0: detailed operation ................................................................... 83 5.5.5 mode 1: detailed operation ................................................................... 84 5.5.6 power-on, reset, and initialization ........................................................85 5.5.6.1 enabling the led interface ....................................................... 85 5.5.7 led data decodes ................................................................................ 86 5.5.7.1 led signaling behavior ............................................................ 86 5.6 cpu interface...................................................................................................... 87 5.6.1 general description ............................................................................... 87 5.6.2 functional description............................................................................ 88 5.6.2.1 read access ............................................................................. 89 5.6.2.2 write access ............................................................................. 90 5.6.2.3 timing parameters ....................................................................91 5.6.3 endian .................................................................................................... 91 5.7 jtag (boundary scan) ....................................................................................... 91
contents datasheet 5 document number: 250210 revision number: 008 revision date: august 10, 2004 5.7.1 tap interface (jtag).............................................................................91 5.7.2 tap state machine ................................................................................92 5.7.3 instruction register and supported instructions ....................................92 5.7.4 id register .............................................................................................92 5.7.5 boundary scan register ........................................................................ 93 5.7.6 bypass register .....................................................................................93 5.8 clocks..................................................................................................................93 5.8.1 system interface reference clocks .......................................................93 5.8.1.1 clk125 .....................................................................................93 5.8.1.2 clk50 .......................................................................................93 5.8.2 spi4-2 receive and transmit data path clocks.................................... 94 5.8.3 jtag clock ............................................................................................94 5.8.4 i 2 c clock ................................................................................................94 5.8.5 led clock ..............................................................................................94 6.0 applications ................................................................................................................ ......95 6.1 power supply sequencing .................................................................................. 95 6.1.1 power-up sequence ..............................................................................95 6.1.2 power-down sequence.......................................................................... 95 6.2 analog power filtering ........................................................................................96 6.3 tx fifo and rx fifo operation........................................................................96 6.3.1 tx fifo..................................................................................................97 6.3.1.1 mac transfer threshold ...........................................................97 6.3.1.2 txfifo relation to spi4-2 transmit fifo status (tstat).......98 6.3.1.3 tx fifo drain (ixf1110 version) .............................................98 6.3.2 rx fifo .................................................................................................99 6.4 reset and initialization ......................................................................................100 6.4.1 spi4-2 initialization...............................................................................100 6.4.1.1 rx spi4-2 ...............................................................................100 6.4.1.2 tx spi4-2................................................................................101 6.4.1.3 serdes ....................................................................................101 6.4.1.4 cpu.........................................................................................101 6.5 serdes power-down capabilities .....................................................................101 6.5.1 placing the serdes port in power-down mode....................................101 6.5.2 bringing the serdes port out of power-down mode ...........................102 6.6 ixf1110 unused ports ...................................................................................... 102 6.7 optical module connections to the ixf1110..................................................... 102 6.7.1 sfp-to-ixf1110 connection ................................................................102 7.0 electrical specifications..................................................................................................1 05 7.1 dc specifications ..............................................................................................107 7.2 undershoot/overshoot specifications ............................................................... 108 7.3 cpu timing specification..................................................................................109 7.4 jtag timing specification ................................................................................111 7.5 transmit pause control timing specifications..................................................112 7.6 optical module interrupt and i 2 c timing specification......................................113 7.7 system timing specifications ...........................................................................116 7.8 led timing specifications ................................................................................117 7.9 serdes timing specification .............................................................................118 7.10 spi4-2 timing specifications ............................................................................120
contents 6 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.0 register definitions ........................................................................................................ 122 8.1 introduction ....................................................................................................... 122 8.2 document structure .......................................................................................... 122 8.3 graphical representation ................................................................................. 122 8.4 per port registers............................................................................................. 124 8.5 memory map ..................................................................................................... 124 8.5.1 mac control registers.........................................................................132 8.5.2 mac rx statistics register overview.................................................. 140 8.5.3 mac tx statistics register overview .................................................. 144 8.5.4 global status and configuration register overview ............................ 148 8.5.5 global rx block register overview..................................................... 153 8.5.6 tx block register overview................................................................. 162 8.5.7 spi4-2 block register overview .......................................................... 172 8.5.8 serdes register overview ..................................................................174 8.5.9 optical module interface block register overview ............................. 176 9.0 package overview ......................................................................................................... 178 9.1 features ............................................................................................................ 178 9.2 ixf1110 package specifics .............................................................................. 178 9.2.1 markings............................................................................................... 179 10.0 product ordering information......................................................................................... 182 figures 1 intel ? ixf1110 mac block diagram ................................................................... 15 2 intel ? ixf1110 mac system block diagram ...................................................... 16 3 552-ball cbga assignments (top view) ............................................................ 17 4 interface diagram................................................................................................ 31 5 packet buffering fifo.........................................................................................47 6 ethernet frame format.......................................................................................47 7 pause frame format ........................................................................................ 48 8 transmit pause control interface ....................................................................... 50 9 spi4-2 interfacing with the network processor or forwarding engine ............... 57 10 data path state ................................................................................................... 59 11 per-port state diagram with transitions at control words ................................. 61 12 dip-4 calculation boundaries ............................................................................. 62 13 dip-4 calculation algorithm ................................................................................ 63 14 fifo status state diagram ................................................................................. 67 15 example of dip-2 encoding ............................................................................... 68 16 data validity timing ............................................................................................ 79 17 start and stop definition timing ......................................................................... 79 18 acknowledge timing ........................................................................................... 80 19 random read ..................................................................................................... 81 20 byte write............................................................................................................82 21 mode 0 timing .................................................................................................... 84 22 mode 1 timing .................................................................................................... 85 23 cpu interface inputs/outputs ............................................................................. 88 24 read timing ? asynchronous interface .............................................................. 90 25 write timing ? asynchronous interface .............................................................. 90 26 power sequencing .............................................................................................. 95
contents datasheet 7 document number: 250210 revision number: 008 revision date: august 10, 2004 27 analog power supply filter network................................................................... 96 28 packet buffering fifo.........................................................................................97 29 sfp-to-ixf1110 connection ............................................................................. 103 30 cpu port read timing......................................................................................109 31 cpu port write timing ......................................................................................109 32 jtag timing .....................................................................................................111 33 transmit pause control interface......................................................................112 34 optical module interrupt timing ........................................................................ 113 35 i 2 c bus timing ..................................................................................................114 36 i 2 c write cycle ..................................................................................................114 37 hardware reset timing.....................................................................................116 38 led timing........................................................................................................117 39 serdes timing...................................................................................................118 40 spi4-2 transmit fifo status bus timing .........................................................120 41 spi4-2 receive fifo status bus timing ..........................................................121 42 memory overview .............................................................................................123 43 register overview .............................................................................................124 44 intel ? ixf1110 mac 552-ceramic ball grid array (cbga) package specifications 180 45 intel ? ixf1110 mac cbga package side view diagram ................................. 181 46 intel ? ixf1110 mac ordering information - sample.........................................182 tables 1 ball list in alphanumeric order by signal name ................................................ 18 2 ball list in alphanumeric order by ball location ................................................ 24 3 spi4-2 interface signal descriptions...................................................................32 4 serdes interface signal descriptions..................................................................34 5 cpu interface signal descriptions ......................................................................35 6 pause control interface signal descriptions....................................................... 36 7 optical module interface signal descriptions...................................................... 37 8 led interface signal descriptions.......................................................................38 9 jtag interface signal descriptions .................................................................... 39 10 system interface signal descriptions..................................................................39 11 power supply signal descriptions ..................................................................... 40 12 unused balls/reserved......................................................................................42 13 pause packets drop enable behavior ................................................................ 45 14 crc errored packets drop enable behavior...................................................... 46 15 valid decodes for txpauseadd[3:0]................................................................49 16 rmon additional statistics registers ................................................................. 54 17 spi4-2 interface signal summary .......................................................................57 18 control word format...........................................................................................60 19 control word definitions .....................................................................................60 20 fifo status format.............................................................................................69 21 serdes driver tx power levels..........................................................................71 22 ixf1110-to-sfp connections ............................................................................. 73 23 led signal descriptions...................................................................................... 83 24 mode 0 clock cycle to data bit relationship...................................................... 84 25 mode 1 clock cycle to data bit relationship...................................................... 85 26 led data decodes..............................................................................................86 27 led behavior ..................................................................................................... 87
contents 8 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 28 cpu interface signals ......................................................................................... 88 29 recommended jtag termination...................................................................... 91 30 supported boundary scan instructions............................................................... 92 31 power sequencing .............................................................................................. 96 32 analog power balls ............................................................................................. 96 33 sfp-to-ixf1110 connection ............................................................................. 103 34 absolute maximum ratings .............................................................................. 105 35 operating conditions .......................................................................................106 36 2.5 v lvttl and cmos i/o electrical characteristics ..................................... 107 37 lvds i/o electrical characteristics................................................................... 107 38 undershoot/overshoot limits............................................................................ 108 39 cpu timing parameters ................................................................................... 109 40 jtag timing parameters.................................................................................. 111 41 transmit pause control interface parameters.................................................. 112 42 optical module interrupt timing parameters .................................................... 113 43 i 2 c ac timing characteristics........................................................................... 114 44 hardware reset timing parameters................................................................. 116 45 led timing parameters.................................................................................... 117 46 transmitter characteristics ............................................................................... 118 47 receiver characteristics ................................................................................... 119 48 spi4-2 transmit fifo status bus timing parameters ..................................... 120 49 spi4-2 receive fifo status bus timing parameters ...................................... 121 50 spi4-2 lvds rise/fall times ........................................................................... 121 51 mac control register map ............................................................................... 124 52 mac rx statistics register map ...................................................................... 125 53 mac tx statistics register map ....................................................................... 126 54 global status and configuration register map................................................. 127 55 rx block register map .....................................................................................128 56 tx block register map .....................................................................................129 57 spi4-2 block register map ............................................................................... 130 58 serdes block register map ............................................................................. 130 59 optical module interface block register map .................................................. 131 60 station address low ($ port_index + 0x00)...................................................... 132 61 station address high ($ port_index + 0x01)..................................................... 132 62 fdfc type ($ port_index + 0x03) ....................................................................132 63 fc tx timer value ($ port_index + 0x07)........................................................ 132 64 fdfc address low ($ port_index + 0x08) ....................................................... 133 65 fdfc address high ($ port_index + 0x09) ......................................................133 66 ipg transmit time ($ port_index + 0x0c)........................................................ 133 67 pause threshold ($ port_index + 0x0e) ........................................................... 134 68 max frame size ($ port_index + 0x0f) ............................................................ 134 69 fc enable ($ port_index + 0x12)...................................................................... 135 70 discard unknown control frame ($ port_index + 0x15) .................................. 135 71 rx config word ($ port_index + 0x16) ............................................................ 135 72 tx config word ($ port_index + 0x17) .............................................................136 73 diverse config ($ port_index + 0x18) .............................................................. 137 74 rx packet filter control ($ port_index + 0x19) ................................................ 138 75 port multicast address low ($ port_index + 0x1a)........................................... 139 76 port multicast address high ($ port_index + 0x1b) .......................................... 139 77 mac rx statistics ($ port_index + 0x20 - port_index + 0x39)......................... 140
contents datasheet 9 document number: 250210 revision number: 008 revision date: august 10, 2004 78 mac tx statistics ($ port_index + 0x40 - port_index + 0x58) ......................... 144 79 port enable ($ 0x500) ....................................................................................... 148 80 link led enable ($ 0x502) ...............................................................................149 81 core clock soft reset ($ 0x504).......................................................................149 82 mac soft reset ($ 0x505) ................................................................................ 150 83 cpu interface ($ 0x508).................................................................................... 150 84 led control ($ 0x509)....................................................................................... 151 85 led flash rate ($ 0x50a) ................................................................................151 86 led fault disable ($ 0x50b).............................................................................151 87 jtag id revision ($ 0x50c) .............................................................................152 88 rx fifo high watermark ports 0 to 9 ($ 0x580 - 0x589)................................. 153 89 rx fifo low watermark ports 0 to 9 ($ 0x58a - 0x593) .................................154 90 rx fifo number of frames removed ports 0 to 9 ($ 0x594 - 0x59d)............156 91 rx fifo port reset ($ 0x59e)..........................................................................158 92 rx fifo errored frame drop enable ($ 0x59f) .............................................. 159 93 rx fifo overflow event ($ 0x5a0) ..................................................................160 94 tx fifo high watermark ports 0 to 9 ($ 0x600 - 0x609) ................................. 162 95 tx fifo low watermark ports 0 to 9 ($ 0x60a - 0x613) ................................. 163 96 tx fifo mac transfer threshold ports 0 to 9 ($ 0x614 - 0x61d) ...................165 97 tx fifo overflow event ($ 0x61e)...................................................................167 98 tx fifo drain ($0x620)....................................................................................168 99 tx fifo info out-of-sequence ($ 0x621) .........................................................169 100 tx fifo number of frames removed ports 0-9 ($ 0x622 - 0x62b) ................ 170 101 spi4-2 rx burst size ($ 0x700)........................................................................172 102 spi4-2 rx training ($ 0x701) ........................................................................... 172 103 spi4-2 rx calendar ($ 0x702).......................................................................... 173 104 spi4-2 tx synchronization ($ 0x703) ...............................................................174 105 serdes tx driver power level ports 0-6 ($ 0x784) .......................................... 174 106 serdes tx driver power level ports 7-9 ($ 0x785) .......................................... 175 107 serdes tx and rx power-down ports 0-9 ($ 0x787) ......................................175 108 optical module status ports 0-9 ($ 0x799) ....................................................... 176 109 optical module control ports 0-9 ($ 0x79a)...................................................... 176 110 i 2 c control ports 0-9 ($ 0x79b) .......................................................................176 111 i 2 c data ports 0-9 ($ 0x79c) ............................................................................177 112 intel ? ixf1110 mac product information.......................................................... 182
contents 10 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 revision history revision number: 008 revision date: august 10, 2004 page # description all globally replaced the following: ?avdd? to ?avdd1p8_1, avdd1p8_2? and ?avdd2? to ?avdd2p5_1, avdd2p5_2?. all globally replaced the following: ?aidd? to ?aidd1p8_1, aidd1p8_2? and ?aidd2? to ?aidd2p5_1, aidd2p5_2?. 32 corrected ball number for rdat15_p from k1 to k12 in table 3 ?spi4-2 interface signal descriptions? . 124 removed short runts threshold register ($ port_index 0x14) and changed to reserved in ?table 51 ?mac control register map? . revision number: 007 revision date: may 5, 2004 page # description 1 changed product ordering number to reflect b2 [hfixf1110cc.b2: 860817]. 41 modified table 11 ?power supply signal descriptions? [changed avdd to avdd1p8_1/2 and avdd2 to avdd2p5_1/2]. 42 added note under section 5.1.2.1, ?padding of undersized frames on transmit?. 42 modified section 5.1.2.3.1, ?filter on unicast packet match? [added text to end of paragraph]. 45 added section 5.1.3, ?flow control?. 66 modified third and fourth paragraphs of section 5.2.2.2, ?calendar_m?. 97 added section 6.2, ?analog power filtering? (ixf1110 only) 116 modified section 6.3.1, ?tx fifo? [added note]. 99 added section 6.3.1.3, ?tx fifo drain (ixf1110 version)?. 110 added table 48 ?spi4-2 lvds rise/fall times?. 126 modified table 72 ?rx packet filter control ($ port_index + 0x19)? (removed table note from the bit 4 description]. 170 modified table 114 ?spi4-2 rx calendar ($ 0x702)? [changed register bits 3:0 to reserved]. 154 modified table 88 ?jtag id revision ($ 0x50c)? [added table note 2]. 163 added table 105 ?tx fifo drain ($0x620)?. 176 modified table 116 ?intel ? ixf1010 mac product information? [changed part number and mm number to reflect b2]. revision number: 006 revision date: december 30, 2003 page # description na deleted old table 19: 1x9-to-ixf1110 connection 136 modified text under section 6.5, ?serdes power-down capabilities (ixf1110 only)?. na changed table 98: tx fifo port reset register (addr: 0x620) to reserved.
contents datasheet 11 document number: 250210 revision number: 008 revision date: august 10, 2004 revision number: 005 (sheet 1 of 2) revision date: november 24, 2003 page # description 1 added product ordering and operating temperature range information, and changed sff-8053, revision 5.5 compatible to sfp msa compatible. 17 deleted old figures 6, 7, and 8 (revision 004) and replaced with figure 6 ?intel ? ixf1110 552-ball cbga assignments (top view)? 18 added new section 3.1, ?intel ? ixf1110 ball list tables? including table 1 ?intel ? ixf1110 ball list in alphanumeric order by signal name? and table 2 ?intel ? ixf1110 ball list in alphanumeric order by ball location?. 30 modified figure 4 ?intel? ixf1110 interface diagram?. 31 broke up old table 3 into table 3 ?intel ? ixf1110 spi4-2 interface signal descriptions? through table 12 ?intel ? ixf1110 system interface signal descriptions?. 34 modified table 5 ?intel ? ixf1110 cpu interface signal descriptions?. 36 modified table 7 ?intel ? ixf1110 optical module interface signal descriptions?. 43 added note under section 5.1.2.3.5, ?filter pause packets?. 43 added note under section 5.1.2.3.6, ?filter crc errored packets?. 44 added third note to section 5.1.3, ?fiber operation?. 46 modified text and added note under section 5.1.4, ?fiber auto-negotiation?. 46 modified section 5.1.5, ?forced mode operation? 52 modified figure 6 ?intel ? ixf1110 spi4-2 interfacing with the network processor or forwarding engine?. 52 added table 17 ?intel ? ixf1110 spi4-2 interface signal summary?. 56 added new section 5.2.1.2, ?eop abort?. 65 globally modified sff-8053, revision 5.5 compatible to sfp msa compatible under section 5.3, ?serdes interface?. 66 modified section 5.3.3, ?functional description?. 66 added section 5.5.4.1 ?transmitter programmable driver-power levels?. 67 added table 21 ?intel ? ixf1110 serdes driver tx power levels?. 68 changed gigabit interface converter section to section 5.6, ?optical module interface?. globally changed gbic to optical module. 69 modified section 5.4.3.2.1, ?mod_def_9:0?. 69 modified section 5.6.3.2.2, ?tx_fault_9:0?. 70 modified section 5.6.3.2.3, ?rx_los_9:0?. 86 added note to ?upx_rdy? under section 5.8.2, ?functional description?. 95 added note under section 6.2.1, ?tx fifo?. 95 added note under section 6.2.1.1, ?mac transfer threshold?. 104 modified/added power consumption max to table 49 ?intel ? ixf1110 operating conditions?. 105 modified table 36 ?intel ? ixf1110 2.5 v lvttl and cmos i/o electrical characteristics?. 105 added section 7.2, ?undershoot/overshoot specifications?. 107 modified table 39 ?intel ? ixf1110 cpu timing parameters?. 115 modified table 46 ?intel ? ixf1110 transmitter characteristics?.
contents 12 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 116 modified table 47 ?intel ? ixf1110 receiver characteristics? (added common mode voltage spec). 119 added caution note under section 8.0, ?register definitions?. 124 modified table 53 ?intel ? ixfixf1110 global status and configuration register map?. 130 modified table 65 ?ipg transmit time register (addr: port_index + 0x0c)?. 131 modified table 66 ?pause threshold register (addr: port_index + 0x0e)?. 132 modified table 68 ?fc enable register (addr: port_index + 0x12)?. 132 modified table 69 ?short runts threshold register (addr: port_index + 0x14)?. 132 modified table 71 ?rx config word register (addr: port_index + 0x16)?. 133 modified table 72 ?tx config word register (addr: port_index + 0x17)?. 134 modified table 73 ?diverse config register (addr: port_index + 0x18)?. 135 modified table 74 ?rx packet filter control register (addr: port_index + 0x19)? (removed note 2 from bit 4, modified bit 5 description). 137 modified table 77 ?mac rx statistics registers (addr: port_index + 0x20 - port_index + 0x39)?. 146 added table 81 ?core clock soft reset register (addr: 0x504)?. 147 added table 82 ?mac soft reset register (addr: 0x505)?. 155 added table 91 ?rx fifo port reset register (addr: 0x59e)?. 165 added section 98, ?tx fifo port reset register (addr: 0x620)?. 167 modified table 100 ?tx fifo number of frames removed ports 0-9 (addr: 0x622 - 0x62b)?. 170 modified table 103 ?spi4-2 rx calendar register (addr: 0x702)?. 171 modified table 104 ?spi4-2 tx synchronization register (addr: 0x703) (b0 silicon revision)?. 173 added table 106 ?serdes tx driver power level ports 0-6 register (addr: 0x784)?. 173 added table 107 ?serdes tx driver power level ports 7-9 register (addr: 0x785)?. revision number: 005 (sheet 2 of 2) revision date: november 24, 2003 page # description
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 13 document number: 250210 revision number: 008 revision date: august 10, 2004 1.0 introduction this document describes the functionality and operation of the intel ? ixf1110 10-port gigabit ethernet media access controller. 1.1 what you will find in this document this document contains the following sections: section 2.0, ?general description? on page 15 intel ? ixf1110 mac block diagram system architecture. section 3.0, ?ball assignments and ball list tables? on page 17 intel ? ixf1110 mac ball grid diagram with two ball list tables (by pin number and signal name) section 4.0, ?ball assignments and signal descriptions? on page 30 signal naming methodology and signal descriptions. section 5.0, ?functional descriptions? on page 43 detailed information about the operation of the intel ? ixf1110 mac including general features, and interface types and descriptions. section 6.0, ?applications? on page 95 discusses the following: ? ?power supply sequencing? ? ?tx fifo and rx fifo operation? ? ?reset and initialization? ? ?optical module connections to the ixf1110? section 7.0, ?electrical specifications? on page 105 information on the product-operating parameters, electrical specifications, and timing parameters. section 8.0, ?register definitions? on page 122 memory map/detailed descriptions and default values for the register set. section 9.0, ?package overview? on page 178 intel ? ixf1110 mac packaging information. section 10.0, ?product ordering information? on page 182 provides a table with part-number information and diagram to order the intel ? ixf1110 mac.
intel ? ixf1110 10-port gigabit ethernet media access controller 14 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 1.2 related documents title document number intel ? ixf1110 mac specification update 251436 intel ? ixf1010 and ixf1110 10-port gigabit ethernet media access controllers design and layout guide 250676 intel ? ixf1110 demo board development kit manual 250807 intel ? spi4 phase 2 performance in gigabit ethernet media access controllers application note 250643 interfacing with the intel ? ixf1010 and intel ? ixf1110 10-port gigabit ethernet media access controllers application note 250856 intel ? ixf1110 thermal design considerations application note 250289 flow control in the intel ? ixf1010 and intel ? ixf1110 10-port gigabit ethernet media access controllers application note 250236
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 15 document number: 250210 revision number: 008 revision date: august 10, 2004 2.0 general description the intel ? ixf1110 is a 10-port 1000 mbps ethernet media access controller (mac). the 10 gigabit interface to the network processor is supported through a system packet interface level 4 phase 2 (spi4-2), and the media interface is an integrated serializer/deserializer (serdes). figure 1 illustrates the ixf1110 block diagram. figure 2 represents the ixf1110 system block diagram. figure 1. intel ? ixf1110 mac block diagram spi4-2 spi4-2 scheduler cpu interface led controller rmon statistics optical module controller ixf1110 serdes 0 serdes 1 serdes 2 serdes 3 serdes 4 serdes 5 serdes 6 serdes 7 serdes 8 serdes 9 mac core rx/tx fifos 0 mac core rx/tx fifos 1 mac core rx/tx fifos 2 mac core rx/tx fifos 3 mac core rx/tx fifos 4 mac core rx/tx fifos 5 mac core rx/tx fifos 6 mac core rx/tx fifos 7 mac core rx/tx fifos 8 mac core rx/tx fifos 9
ixf1010 and ixf1110 10-port 100/1000 mbps ethernet media access controllerintel ? ixf1110 10- 16 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 figure 2. intel ? ixf1110 mac system block diagram ixf1110 cpu led serial-to-parallel converter up if led serial interface port 0 optics module port 1 optics module port 2 optics module port 3 optics module port 4 optics module port 5 optics module port 6 optics module port 7 optics module port 8 optics module port 9 optics module serdes/optical module interface forwarding engine network processor spi4-2
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 17 document number: 250210 revision number: 008 revision date: august 10, 2004 3.0 ball assignments and ball list tables figure 3 illustrates the ixf1110 552-ball cbga assignments. table 1 and table 2 provide ball list tables in alphanumeric order by signal name and ball location under section 3.1, ?ball list tables? on page 18 . figure 3. 552-ball cbga assignments (top view) b2510-01 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad a b c d e f g h j k l m n p r t u v w y aa ab ac ad 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a5 a4 a3 a2 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b5 b4 b3 b2 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c5 c4 c3 c2 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d5 d4 d3 d2 e6 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 e19 e20 e21 e22 e23 e24 e5 e4 e3 e2 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 f5 f4 f3 f2 g6 g7 g8 g9 g10 g11 g12 g13 g14 g15 g16 g17 g18 g19 g20 g21 g22 g23 g24 g5 g4 g3 g2 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h5 h4 h3 h2 j6 j7 j8 j9 j10 j11 j12 j13 j14 j15 j16 j17 j18 j19 j20 j21 j22 j23 j24 j5 j4 j3 j2 a1 b1 c1 d1 e1 f1 g1 h1 j1 k1 l1 m1 n1 l1 r1 t1 u1 v1 w1 y1 aa1 ab1 ac1 ad1 k6 k7 k8 k9 k10 k11 k12 k13 k14 k15 k16 k17 k18 k19 k20 k21 k22 k23 k24 k5 k4 k3 k2 l6 l7 l8 l9 l10 l11 l12 l13 l14 l15 l16 l17 l18 l19 l20 l21 l22 l23 l24 l5 l4 l3 l2 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 m16 m17 m18 m19 m20 m21 m22 m23 m24 m5 m4 m3 m2 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n22 n23 n24 n5 n4 n3 n2 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 p5 p4 p3 p2 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r5 r4 r3 r2 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t5 t4 t3 t2 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u23 u24 u5 u4 u3 u2 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 v21 v22 v23 v24 v5 v4 v3 v2 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 w19 w20 w21 w22 w23 w24 w5 w4 w3 w2 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23 y24 y5 y4 y3 y2 aa6 aa7 aa8 aa9 aa10 aa11 aa12 aa13 aa14 aa15 aa16 aa17 aa18 aa19 aa20 aa21 aa22 aa23 aa24 aa5 aa4 aa3 aa2 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 ab19 ab20 ab21 ab22 ab23 ab24 ab5 ab4 ab3 ab2 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad5 ad4 ad3 ad2 ac6 ac7 ac8 ac9 ac10 ac11 ac12 ac13 ac14 ac15 ac16 ac17 ac18 ac19 ac20 ac21 ac22 ac23 ac24 ac5 ac4 ac3 ac2
intel ? ixf1110 10-port gigabit ethernet media access controller 18 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 3.1 ball list tables ball list tables are provided in alphanumeric order by signal name ( table 1 ) and by ball location order ( table 2 ). note: intel recommends that all unconnected balls be tied to their inactive states through external pull-ups or pull-downs. 3.1.1 balls listed in alphanumeric order by signal name table 1 shows the ball locations and signal names arranged in alphanumeric order by signal name. table 1. ball list in alphanumeric order by signal name signal ball avdd1p8_1 d1 avdd1p8_1 e24 avdd1p8_2 p7 avdd1p8_2 p18 avdd1p8_2 v6 avdd1p8_2 v11 avdd1p8_2 v14 avdd1p8_2 v18 avdd2p5_1 y1 avdd2p5_2 n3 avdd2p5_2 n22 avdd2p5_2 p3 avdd2p5_2 p22 avdd2p5_2 v10 avdd2p5_2 v15 clk125 aa5 clk50 c21 gnd b6 gnd b10 gnd b15 gnd b19 gnd c4 gnd d4 gnd d5 gnd d8 gnd d12 gnd d13 gnd d17 gnd d21 gnd d22 gnd d24 gnd e1 gnd f2 gnd f6 gnd f10 gnd f15 gnd f19 gnd f23 gnd g10 gnd h4 gnd h8 gnd h12 gnd h13 gnd h17 gnd h21 gnd j10 gnd j15 gnd j21 gnd j23 gnd k2 gnd k6 gnd k9 gnd k11 gnd k14 gnd k16 gnd k19 signal ball gnd k20 gnd k23 gnd k24 gnd l3 gnd l6 gnd l10 gnd l12 gnd l13 gnd l15 gnd l24 gnd m3 gnd m4 gnd m8 gnd m11 gnd m14 gnd m17 gnd m18 gnd m21 gnd n4 gnd n8 gnd n11 gnd n14 gnd n17 gnd n21 gnd p1 gnd p10 gnd p12 gnd p13 signal ball
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 19 document number: 250210 revision number: 008 revision date: august 10, 2004 gnd p15 gnd p21 gnd p23 gnd p24 gnd r1 gnd r2 gnd r3 gnd r6 gnd r9 gnd r10 gnd r11 gnd r14 gnd r16 gnd r19 gnd r23 gnd r24 gnd t7 gnd t8 gnd t9 gnd t10 gnd t15 gnd t17 gnd t18 gnd t19 gnd t21 gnd t23 gnd u4 gnd u7 gnd u8 gnd u12 gnd u13 gnd u16 gnd u17 gnd u21 gnd v2 gnd v3 gnd v13 gnd v16 gnd w2 signal ball gnd w3 gnd w5 gnd w6 gnd w7 gnd w10 gnd w15 gnd w19 gnd w20 gnd w23 gnd y2 gnd y3 gnd y8 gnd y12 gnd y13 gnd y15 gnd y16 gnd y18 gnd aa1 gnd aa3 gnd aa4 gnd aa7 gnd aa8 gnd aa12 gnd aa13 gnd aa14 gnd aa17 gnd aa21 gnd ab6 gnd ab7 gnd ab10 gnd ab17 gnd ab21 gnd ab23 gnd ac6 gnd ac7 gnd ac10 gnd ac11 gnd ac15 gnd ac19 signal ball gnd ac20 gnd ad21 i 2 c_clk l19 i 2 c_data_0 g22 i 2 c_data_1 g23 i 2 c_data_2 j24 i 2 c_data_3 f22 i 2 c_data_4 e23 i 2 c_data_5 h24 i 2 c_data_6 g20 i 2 c_data_7 e22 i 2 c_data_8 g24 i 2 c_data_9 f24 led_clk a19 led_data a20 led_latch k18 mod_def_0 n24 mod_def_1 y21 mod_def_2 aa16 mod_def_3 m20 mod_def_4 ac14 mod_def_5 u11 mod_def_6 t4 mod_def_7 ab2 mod_def_8 r7 mod_def_9 l1 mod_def_int g15 nc a5 nc a6 nc c10 nc c15 nc g7 nc g8 nc h22 nc j22 nc k7 nc l21 nc l23 nc m1 signal ball
intel ? ixf1110 10-port gigabit ethernet media access controller 20 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 nc m7 nc n1 nc n5 nc n7 nc n20 nc p4 nc p5 nc p6 nc p17 nc p19 nc p20 nc r5 nc r13 nc r18 nc r20 nc r22 nc t1 nc t6 nc u1 nc v1 nc v8 nc v9 nc v19 nc w1 nc w16 nc w18 nc y7 nc y10 nc y11 nc y14 nc aa11 nc aa20 nc aa22 nc ab3 nc ab5 nc ab8 nc ab18 nc ab19 nc ab20 signal ball nc ab22 nc ad4 nc ad5 nc ad6 nc ad7 nc ad8 nc ad17 nc ad19 nc ad20 no ball a2 no ball a3 no ball a22 no ball a23 no ball a24 no ball b1 no ball b2 no ball b23 no ball b24 no ball c1 no ball c24 no ball ab1 no ball ab24 no ball ac1 no ball ac2 no ball ac23 no ball ac24 no ball ad1 no ball ad2 no ball ad3 no ball ad22 no ball ad23 no ball ad24 no pad a1 rctl_n h18 rctl_p h16 rdat0_n e20 rdat0_p e19 rdat1_n c20 rdat1_p b20 signal ball rdat2_n g19 rdat2_p f18 rdat3_n h20 rdat3_p g21 rdat4_n j19 rdat4_p j18 rdat5_n l18 rdat5_p l17 rdat6_n e17 rdat6_p e16 rdat7_n n15 rdat7_p m15 rdat8_n d16 rdat8_p c16 rdat9_n e18 rdat9_p d18 rdat10_n g18 rdat10_p g17 rdat11_n k15 rdat11_p j16 rdat12_n a14 rdat12_p a13 rdat13_n e14 rdat13_p e13 rdat14_n g16 rdat14_p f16 rdat15_n k13 rdat15_p k12 rdclk_n c19 rdclk_p c18 rsclk j17 rstat0 l20 rstat1 j20 rx_los_0 l22 rx_los_1 v17 rx_los_2 ad18 rx_los_3 r12 rx_los_4 ab15 rx_los_5 v12 signal ball
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 21 document number: 250210 revision number: 008 revision date: august 10, 2004 rx_los_6 y9 rx_los_7 ac3 rx_los_8 t2 rx_los_9 p2 rx_los_int b14 rx_n_0 u22 rx_n_1 u20 rx_n_2 t24 rx_n_3 v24 rx_n_4 ab14 rx_n_5 ad14 rx_n_6 ac16 rx_n_7 ad15 rx_n_8 v4 rx_n_9 y5 rx_p_0 t22 rx_p_1 t20 rx_p_2 u24 rx_p_3 w24 rx_p_4 ab13 rx_p_5 ad13 rx_p_6 ab16 rx_p_7 ad16 rx_p_8 v5 rx_p_9 y6 sys_res_l y4 tck aa24 tctl_n n10 tctl_p m10 tdat0_n j5 tdat0_p j6 tdat1_n j3 tdat1_p h3 tdat2_p b5 tdat3_n h9 tdat3_p g9 tdat4_p f7 tdat4_p g6 tdat5_n h5 signal ball tdat5_p g5 tdat6_n l7 tdat6_p l8 tdat7_n c6 tdat7_p c7 tdat8_n m5 tdat8_p l5 tdat9_n c8 tdat9_p b7 tdat10_n f9 tdat10_p e9 tdat11_n e7 tdat11_p e8 tdat12_n j8 tdat12_p h7 tdat13_n k10 tdat13_p j9 tdat14_n d9 tdat14_p c9 tdat15_n h11 tdat15_p g11 tdat2_n c5 tdclk- e4 tdclk_p d3 tdi ac18 tdo y24 tms t16 trst_l n18 tsclk c11 tstat0 e5 tstat1 e6 tx_disable_0 k22 tx_disable_1 m22 tx_disable_2 ac22 tx_disable_3 u18 tx_disable_4 u14 tx_disable_5 aa18 tx_disable_6 u9 tx_disable_7 aa9 signal ball tx_disable_8 v7 tx_disable_9 l4 tx_fault_0 m24 tx_fault_1 v23 tx_fault_2 y17 tx_fault_3 r15 tx_fault_4 w14 tx_fault_5 w11 tx_fault_6 w9 tx_fault_7 ac5 tx_fault_8 p8 tx_fault_9 l2 tx_fault_int b11 tx_n_0 v21 tx_n_1 y20 tx_n_2 w22 tx_n_3 y22 tx_n_4 ab11 tx_n_5 ad11 tx_n_6 ac9 tx_n_7 ad10 tx_n_8 u3 tx_n_9 u5 tx_p_0 v20 tx_p_1 y19 tx_p_2 v22 tx_p_3 y23 tx_p_4 ab12 tx_p_5 ad12 tx_p_6 ab9 tx_p_7 ad9 tx_p_8 t3 tx_p_9 t5 txpauseadd0 g3 txpauseadd1 g2 txpauseadd2 j2 txpauseadd3 k1 txpausefr j7 upx_add0 j1 signal ball
intel ? ixf1110 10-port gigabit ethernet media access controller 22 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 upx_add2 f3 upx_add3 h1 upx_add4 e3 upx_add5 e2 upx_add6 g1 upx_add7 c3 upx_add8 f5 upx_add9 f1 upx_add1 g4 upx_add10 c2 upx_cs_l f20 upx_data0 b3 upx_data1 a4 upx_data2 b9 upx_data3 a7 upx_data4 c12 upx_data5 e11 upx_data6 c13 upx_data7 a8 upx_data8 a10 upx_data9 a9 upx_data10 e12 upx_data11 a11 upx_data12 g12 upx_data13 e10 upx_data14 f11 upx_data15 d7 upx_data16 d14 upx_data17 c14 upx_data18 f14 upx_data19 a12 upx_data20 a15 upx_data21 g13 upx_data22 b16 upx_data23 e15 upx_data24 g14 upx_data25 a16 upx_data26 c17 upx_data27 a17 signal ball upx_data28 b18 upx_data29 a21 upx_data30 b22 upx_data31 c23 upx_rd_l h14 upx_rdy_l c22 upx_wr_l a18 vdd d6 vdd d10 vdd d11 vdd d15 vdd d19 vdd d20 vdd e21 vdd f4 vdd f21 vdd h10 vdd h15 vdd j4 vdd j11 vdd j14 vdd k3 vdd k4 vdd k5 vdd k8 vdd k17 vdd k21 vdd l9 vdd l11 vdd l14 vdd l16 vdd p9 vdd p11 vdd p14 vdd p16 vdd r4 vdd r8 vdd r17 vdd r21 signal ball vdd t11 vdd t14 vdd u10 vdd u15 vdd w4 vdd w21 vdd aa6 vdd aa10 vdd aa15 vdd aa19 vdd ab4 vdd2 b4 vdd2 b8 vdd2 b12 vdd2 b13 vdd2 b17 vdd2 b21 vdd2 d2 vdd2 d23 vdd2 f8 vdd2 f12 vdd2 f13 vdd2 f17 vdd2 h2 vdd2 h6 vdd2 h19 vdd2 h23 vdd2 j12 vdd2 j13 vdd2 m2 vdd2 m6 vdd2 m9 vdd2 m12 vdd2 m13 vdd2 m16 vdd2 m19 vdd2 m23 vdd2 n2 vdd2 n6 signal ball
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 23 document number: 250210 revision number: 008 revision date: august 10, 2004 vdd2 n9 vdd2 n12 vdd2 n13 vdd2 n16 vdd2 n19 vdd2 n23 vdd2 t12 vdd2 t13 vdd2 u2 vdd2 u6 vdd2 u19 vdd2 u23 vdd2 w8 vdd2 w12 vdd2 w13 vdd2 w17 vdd2 aa2 vdd2 aa23 vdd2 ac4 vdd2 ac8 vdd2 ac12 vdd2 ac13 vdd2 ac17 vdd2 ac21 signal ball
intel ? ixf1110 10-port gigabit ethernet media access controller 24 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 3.1.2 balls listed in alphanumeric order by ball location table 2 shows the ball locations and signal names arranged in alphanumeric order by ball location. note: intel recommends that all unconnected balls be tied to their inactive states through external pull- ups or pull-downs. table 2. ball list in alphanumeric order by ball location ball signal a1 no pad a2 no ball a3 no ball a4 upx_data1 a5 nc a6 nc a7 upx_data3 a8 upx_data7 a9 upx_data9 a10 upx_data8 a11 upx_data11 a12 upx_data19 a13 rdat12_p a14 rdat12_n a15 upx_data20 a16 upx_data25 a17 upx_data27 a18 upx_wr_l a19 led_clk a20 led_data a21 upx_data29 a22 no ball a23 no ball a24 no ball b1 no ball b2 no ball b3 upx_data0 b4 vdd2 b5 tdat2_p b6 gnd b7 tdat9_p b8 vdd2 b9 upx_data2 b10 gnd b11 tx_fault_int b12 vdd2 b13 vdd2 b14 rx_los_int b15 gnd b16 upx_data22 b17 vdd2 b18 upx_data28 b19 gnd b20 rdat1_p b21 vdd2 b22 upx_data30 b23 no ball b24 no ball c1 no ball c2 upx_add10 c3 upx_add7 c4 gnd c5 tdat2_n c6 tdat7_n c7 tdat7_p c8 tdat9_n c9 tdat14_p c10 nc c11 tsclk c12 upx_data4 c13 upx_data6 c14 upx_data17 c15 nc c16 rdat8_p ball signal c17 upx_data26 c18 rdclk_p c19 rdclk_n c20 rdat1_n c21 clk50 c22 upx_rdy_l c23 upx_data31 c24 no ball d1 avdd1p8_1 d2 vdd2 d3 tdclk_p d4 gnd d5 gnd d6 vdd d7 upx_data15 d8 gnd d9 tdat14_n d10 vdd d11 vdd d12 gnd d13 gnd d14 upx_data16 d15 vdd d16 rdat8_n d17 gnd d18 rdat9_p d19 vdd d20 vdd d21 gnd d22 gnd d23 vdd2 d24 gnd ball signal
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 25 document number: 250210 revision number: 008 revision date: august 10, 2004 e1 gnd e2 upx_add5 e3 upx_add4 e4 tdclk- e5 tstat0 e6 tstat1 e7 tdat11_n e8 tdat11_p e9 tdat10_p e10 upx_data13 e11 upx_data5 e12 upx_data10 e13 rdat13_p e14 rdat13_n e15 upx_data23 e16 rdat6_p e17 rdat6_n e18 rdat9_n e19 rdat0_p e20 rdat0_n e21 vdd e22 i 2 c_data_7 e23 i 2 c_data_4 e24 avdd1p8_1 f1 upx_add9 f2 gnd f3 upx_add2 f4 vdd f5 upx_add8 f6 gnd f7 tdat4_p f8 vdd2 f9 tdat10_n f10 gnd f11 upx_data14 f12 vdd2 f13 vdd2 f14 upx_data18 f15 gnd ball signal f16 rdat14_p f17 vdd2 f18 rdat2_p f19 gnd f20 upx_cs_l f21 vdd f22 i 2 c_data_3 f23 gnd f24 i 2 c_data_9 g1 upx_add6 g2 txpauseadd1 g3 txpauseadd0 g4 upx_add1 g5 tdat5_p g6 tdat4_p g7 nc g8 nc g9 tdat3_p g10 gnd g11 tdat15_p g12 upx_data12 g13 upx_data21 g14 upx_data24 g15 mod_def_int g16 rdat14_n g17 rdat10_p g18 rdat10_n g19 rdat2_n g20 i 2 c_data_6 g21 rdat3_p g22 i 2 c_data_0 g23 i 2 c_data_1 g24 i 2 c_data_8 h1 upx_add3 h2 vdd2 h3 tdat1_p h4 gnd h5 tdat5_n h6 vdd2 ball signal h7 tdat12_p h8 gnd h9 tdat3_n h10 vdd h11 tdat15_n h12 gnd h13 gnd h14 upx_rd_l h15 vdd h16 rctl_p h17 gnd h18 rctl_n h19 vdd2 h20 rdat3_n h21 gnd h22 nc h23 vdd2 h24 i 2 c_data_5 j1 upx_add0 j2 txpauseadd2 j3 tdat1_n j4 vdd j5 tdat0_n j6 tdat0_p j7 txpausefr j8 tdat12_n j9 tdat13_p j10 gnd j11 vdd j12 vdd2 j13 vdd2 j14 vdd j15 gnd j16 rdat11_p j17 rsclk j18 rdat4_p j19 rdat4_n j20 rstat1 j21 gnd ball signal
intel ? ixf1110 10-port gigabit ethernet media access controller 26 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 j22 nc j23 gnd j24 i 2 c_data_2 k1 txpauseadd3 k2 gnd k3 vdd k4 vdd k5 vdd k6 gnd k7 nc k8 vdd k9 gnd k10 tdat13_n k11 gnd k12 rdat15_p k13 rdat15_n k14 gnd k15 rdat11_n k16 gnd k17 vdd k18 led_latch k19 gnd k20 gnd k21 vdd k22 tx_disable_0 k23 gnd k24 gnd l1 mod_def_9 l2 tx_fault_9 l3 gnd l4 tx_disable_9 l5 tdat8_p l6 gnd l7 tdat6_n l8 tdat6_p l9 vdd l10 gnd l11 vdd l12 gnd ball signal l13 gnd l14 vdd l15 gnd l16 vdd l17 rdat5_p l18 rdat5_n l19 i 2 c_clk l20 rstat0 l21 nc l22 rx_los_0 l23 nc l24 gnd m1 nc m2 vdd2 m3 gnd m4 gnd m5 tdat8_n m6 vdd2 m7 nc m8 gnd m9 vdd2 m10 tctl_p m11 gnd m12 vdd2 m13 vdd2 m14 gnd m15 rdat7_p m16 vdd2 m17 gnd m18 gnd m19 vdd2 m20 mod_def_3 m21 gnd m22 tx_disable_1 m23 vdd2 m24 tx_fault_0 n1 nc n2 vdd2 n3 avdd2p5_2 ball signal n4 gnd n5 nc n6 vdd2 n7 nc n8 gnd n9 vdd2 n10 tctl_n n11 gnd n12 vdd2 n13 vdd2 n14 gnd n15 rdat7_n n16 vdd2 n17 gnd n18 trst_l n19 vdd2 n20 nc n21 gnd n22 avdd2p5_2 n23 vdd2 n24 mod_def_0 p1 gnd p2 rx_los_9 p3 avdd2p5_2 p4 nc p5 nc p6 nc p7 avdd1p8_2 p8 tx_fault_8 p9 vdd p10 gnd p11 vdd p12 gnd p13 gnd p14 vdd p15 gnd p16 vdd p17 nc p18 avdd1p8_2 ball signal
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 27 document number: 250210 revision number: 008 revision date: august 10, 2004 p19 nc p20 nc p21 gnd p22 avdd2p5_2 p23 gnd p24 gnd r1 gnd r2 gnd r3 gnd r4 vdd r5 nc r6 gnd r7 mod_def_8 r8 vdd r9 gnd r10 gnd r11 gnd r12 rx_los_3 r13 nc r14 gnd r15 tx_fault_3 r16 gnd r17 vdd r18 nc r19 gnd r20 nc r21 vdd r22 nc r23 gnd r24 gnd t1 nc t2 rx_los_8 t3 tx_p_8 t4 mod_def_6 t5 tx_p_9 t6 nc t7 gnd t8 gnd t9 gnd ball signal t10 gnd t11 vdd t12 vdd2 t13 vdd2 t14 vdd t15 gnd t16 tms t17 gnd t18 gnd t19 gnd t20 rx_p_1 t21 gnd t22 rx_p_0 t23 gnd t24 rx_n_2 u1 nc u2 vdd2 u3 tx_n_8 u4 gnd u5 tx_n_9 u6 vdd2 u7 gnd u8 gnd u9 tx_disable_6 u10 vdd u11 mod_def_5 u12 gnd u13 gnd u14 tx_disable_4 u15 vdd u16 gnd u17 gnd u18 tx_disable_3 u19 vdd2 u20 rx_n_1 u21 gnd u22 rx_n_0 u23 vdd2 u24 rx_p_2 ball signal v1 nc v2 gnd v3 gnd v4 rx_n_8 v5 rx_p_8 v6 avdd1p8_2 v7 tx_disable_8 v8 nc v9 nc v10 avdd2p5_2 v11 avdd1p8_2 v12 rx_los_5 v13 gnd v14 avdd1p8_2 v15 avdd2p5_2 v16 gnd v17 rx_los_1 v18 avdd1p8_2 v19 nc v20 tx_p_0 v21 tx_n_0 v22 tx_p_2 v23 tx_fault_1 v24 rx_n_3 w1 nc w2 gnd w3 gnd w4 vdd w5 gnd w6 gnd w7 gnd w8 vdd2 w9 tx_fault_6 w10 gnd w11 tx_fault_5 w12 vdd2 w13 vdd2 w14 tx_fault_4 w15 gnd ball signal
intel ? ixf1110 10-port gigabit ethernet media access controller 28 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 w16 nc w17 vdd2 w18 nc w19 gnd w20 gnd w21 vdd w22 tx_n_2 w23 gnd w24 rx_p_3 y1 avdd2p5_1 y2 gnd y3 gnd y4 sys_res_l y5 rx_n_9 y6 rx_p_9 y7 nc y8 gnd y9 rx_los_6 y10 nc y11 nc y12 gnd y13 gnd y14 nc y15 gnd y16 gnd y17 tx_fault_2 y18 gnd y19 tx_p_1 y20 tx_n_1 y21 mod_def_1 y22 tx_n_3 y23 tx_p_3 y24 tdo aa1 gnd aa2 vdd2 aa3 gnd aa4 gnd aa5 clk125 aa6 vdd ball signal aa7 gnd aa8 gnd aa9 tx_disable_7 aa10 vdd aa11 nc aa12 gnd aa13 gnd aa14 gnd aa15 vdd aa16 mod_def_2 aa17 gnd aa18 tx_disable_5 aa19 vdd aa20 nc aa21 gnd aa22 nc aa23 vdd2 aa24 tck ab1 no ball ab2 mod_def_7 ab3 nc ab4 vdd ab5 nc ab6 gnd ab7 gnd ab8 nc ab9 tx_p_6 ab10 gnd ab11 tx_n_4 ab12 tx_p_4 ab13 rx_p_4 ab14 rx_n_4 ab15 rx_los_4 ab16 rx_p_6 ab17 gnd ab18 nc ab19 nc ab20 nc ab21 gnd ball signal ab22 nc ab23 gnd ab24 no ball ac1 no ball ac2 no ball ac3 rx_los_7 ac4 vdd2 ac5 tx_fault_7 ac6 gnd ac7 gnd ac8 vdd2 ac9 tx_n_6 ac10 gnd ac11 gnd ac12 vdd2 ac13 vdd2 ac14 mod_def_4 ac15 gnd ac16 rx_n_6 ac17 vdd2 ac18 tdi ac19 gnd ac20 gnd ac21 vdd2 ac22 tx_disable_2 ac23 no ball ac24 no ball ad1 no ball ad2 no ball ad3 no ball ad4 nc ad5 nc ad6 nc ad7 nc ad8 nc ad9 tx_p_7 ad10 tx_n_7 ad11 tx_n_5 ad12 tx_p_5 ball signal
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 29 document number: 250210 revision number: 008 revision date: august 10, 2004 ad13 rx_p_5 ad14 rx_n_5 ad15 rx_n_7 ad16 rx_p_7 ad17 nc ad18 rx_los_2 ad19 nc ad20 nc ad21 gnd ad22 no ball ad23 no ball ad24 no ball ball signal
intel ? ixf1110 10-port gigabit ethernet media access controller 30 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 4.0 ball assignments and signal descriptions 4.1 naming conventions 4.1.1 signal name conventions signal names begin with a signal mnemonic, and can also contain one or more of the following designations: a differential pair designation, a serial designation, and an active low designation. signal naming conventions are as follows: differential pair + port designation. the positive and negative components of differential pairs tied to a specific port are designated by the signal mnemonic, immediately followed by an underscore and either p (positive component) or n (negative component), and an underscore followed by the port designation. for example, serdes interface signals for port 0 are identified as tx_p_0 and tx_n_0. serial designation. a set of signals that are not tied to any specific port are designated by the signal mnemonic, followed by a bracketed serial designation. for example, the set of 11 cpu address bus signals is identified as upx_add[10:0]. port designation . individual signals that apply to a particular port are designated by the signal mnemonic, immediately followed by an underscore and the port designation. for example, optical module i 2 c serial data signals would be identified as i 2 c_data_0, i 2 c_data_1, etc. active low designation. a control input or indicator output that is active low is designated by a final suffix consisting of an underscore followed by an upper case ?l?. for example, the cpu cycle complete identifier is shown as upx_rdy_l. 4.1.2 register address conventions registers located in on-chip memory are accessed using a register address, which is provided in hex notation. a register address is indicated by the dollar sign ($), followed by the memory location in hex.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 31 document number: 250210 revision number: 008 revision date: august 10, 2004 4.2 interface signal groups this section describes the ixf1110 signals in groups according to the associated interface or function. figure 4 and table 3, ?spi4-2 interface signal descriptions? through table 12, ?unused balls/reserved? describe the signals used by the ixf1110. figure 4. interface diagram intel ? ixf1110 tdat[15:0]_p/n tdo rsclk rctl_p/n rdclk_p/n rstat[1:0] rdat[15:0]_p/n tsclk tctl_p/n tdclk_p/n tstat[1:0] upx_add[10:0] upx_data[31:0] txpausefr txpauseadd[3:0] tclk tdi tms upx_wr_l upx_rd_l upx_cs_l upx_rdy_l serdes interface jtag interface cpu interface rx_p/n_0:9 spi4-2 interface tx_p/n_0:9 p ause control interface optica l modul e interfac e mod_def_0:9 tx_disable_0:9 tx_fault_0:9 rx_los_0:9 tx_fault_int rx_los_int mod_def_int i 2 c_clk i 2 c_data_0:9 led interface led_clk led_latch led_data clk125 system interface clk50 sys_res_l b2585-02 trst_l
intel ? ixf1110 10-port gigabit ethernet media access controller 32 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 3. spi4-2 interface signal descriptions (sheet 1 of 2) signal name ball designator type standard signal description tdat15_p, tdat15_n tdat14_p, tdat14_n tdat13_p, tdat13_n tdat12_p, tdat12_n tdat11_p, tdat11_n tdat10_p, tdat10_n tdat9_p, tdat9_n tdat8_p, tdat8_n tdat7_p, tdat7_n tdat6_p, tdat6_n tdat5_p, tdat5_n tdat4_p, tdat4_n tdat3_p, tdat3_n tdat2_p, tdat2_n tdat1_p, tdat1_n tdat0_p, tdat0_n g11 c9 j9 h7 e8 e9 b7 l5 c7 l8 g5 f7 g9 b5 h3 j6 h11 d9 k10 j8 e7 f9 c8 m5 c6 l7 h5 g6 h9 c5 j3 j5 input lvds transmit data bus: carries payload data and in-band control words to the ixf1110 link-layer device. internally terminated differentially with 100 ?. tdclk_p tdclk_n d3 e4 input lvds transmit data clock: clock associated with tdat[15:0] and tctl. data and control lines are driven off the rising and falling edges of the clock. internally terminated differentially with 100 ?. note: if tdclk is applied to the ixf1110 after the device has come out of reset, the system designer must ensure the tdclk is stable when applied. failure to due so can result in the ixf1110 training on a non-stable clock, causing dip4 errors and data corruption. tctl_p tctl_n m10 n10 input lvds transmit control: tctl is high when a control word is present on tdat[15:0]. otherwise, tctl is low. internally terminated differentially with 100 ?. tsclk c11 output 2.5 v lvttl transmit status clock: clock associated with tstat [1:0]. frequency is equal to one-quarter tdclk. tstat1 tstat0 e6 e5 output 2.5 v lvttl transmit fifo status: carries round-robin fifo status information, along with associated error detection and framing.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 33 document number: 250210 revision number: 008 revision date: august 10, 2004 rdat15_p, rdat15_n rdat14_p, rdat14_n rdat13_p, rdat13_n rdat12_p, rdat12_n rdat11_p, rdat11_n rdat10_p, rdat10_n rdat9_p, rdat9_n rdat8_p, rdat8_n rdat7_p, rdat7_n rdat6_p, rdat6_n rdat5_p, rdat5_n rdat4_p, rdat4_n rdat3_p, rdat3_n rdat2_p, rdat2_n- rdat1_p, rdat1_n rdat0_p, rdat0_n k12 f16 e13 a13 j16 g17 d18 c16 m15 e16 l17 j18 g21 f18 b20 e19 k13 g16 e14 a14 k15 g18 e18 d16 n15 e17 l18 j19 h20 g19 c20 e20 output lvds receive data: carries payload data and in-band control from the ixf1110 link-layer device. internally terminated differentially with 100 ?. rdclk_p rdclk_n c18 c19 output lvds receive data clock: clock associated with rdat[15:0] and rctl. data and control lines are driven off the rising and falling edges of the clock. the frequency range is 320-400 mhz. frequency is always a multiplied- by-8 version of the clk50 reference clock. internally terminated differentially with 100 ?. rctl_p rctl_n h16 h18 output lvds receive control: rctl is high when a control word is present on rdat[15:0]. otherwise, rctl is low. internally terminated differentially with 100 ?. rsclk j17 input 2.5 v lvttl receive status clock: the clock associated with rstat[1:0]. rstat1 rstat0 j20 l20 input 2.5 v lvttl receive fifo status: carries round-robin fifo status information, along with associated error detection and framing. table 3. spi4-2 interface signal descriptions (sheet 2 of 2) signal name ball designator type standard signal description
intel ? ixf1110 10-port gigabit ethernet media access controller 34 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 4. serdes interface signal descriptions signal name ball designator type standard signal description tx_p_0, tx_n_0 tx_p_1, tx_n_1 tx_p_2, tx_n_2 tx_p_3, tx_n_3 tx_p_4, tx_n_4 tx_p_5, tx_n_5 tx_p_6, tx_n_6 tx_p_7, tx_n_7 tx_p_8, tx_n_8 tx_p_9, tx_n_9 v20 y19 v22 y23 ab12 ad12 ab9 ad9 t3 t5 v21 y20 w22 y22 ab11 ad11 ac9 ad10 u3 u5 output serdes transmit differential output: carries the 1.25 ghz data to the optics module. rx_p_0, rx_n_0 rx_p_1, rx_n_1 rx_p_2, rx_n_2 rx_p_3, rx_n_3 rx_p_4, rx_n_4 rx_p_5, rx_n_5 rx_p_6, rx_n_6 rx_p_7, rx_n_7 rx_p_8, rx_n_8 rx_p_9, rx_n_9 t22 t20 u24 w24 ab13 ad13 ab16 ad16 v5 y6 u22 u20 t24 v24 ab14 ad14 ac16 ad15 v4 y5 input serdes receive differential input: carries the 1.25 ghz data from the optics module. internally terminated differentially with 100 ? .
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 35 document number: 250210 revision number: 008 revision date: august 10, 2004 table 5. cpu interface signal descriptions (sheet 1 of 2) signal name ball designator type standard signal description upx_add10 upx_add9 upx_add8 upx_add7 upx_add6 upx_add5 upx_add4 upx_add3 upx_add2 upx_add1 upx_add0 c2 f1 f5 c3 g1 e2 e3 h1 f3 g4 j1 input 2.5 v cmos address bus: 11-bit address bus upx_cs_l f20 input 2.5 v cmos chip select signal: active low chip select upx_data31 upx_data30 upx_data29 upx_data28 upx_data27 upx_data26 upx_data25 upx_data24 upx_data23 upx_data22 upx_data21 upx_data20 upx_data19 upx_data18 upx_data17 upx_data16 upx_data15 upx_data14 upx_data13 upx_data12 upx_data11 upx_data10 upx_data9 upx_data8 upx_data7 upx_data6 upx_data5 upx_data4 upx_data3 upx_data2 upx_data1 upx_data0 c23 b22 a21 b18 a17 c17 a16 g14 e15 b16 g13 a15 a12 f14 c14 d14 d7 f11 e10 g12 a11 e12 a9 a10 a8 c13 e11 c12 a7 b9 a4 b3 input/ output 2.5 v cmos bi-directional data bus: 32-bit bi- directional data bus 1. this i/o meets the 2.5 v cmos specification only during boundary scan mode.
intel ? ixf1110 10-port gigabit ethernet media access controller 36 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 upx_wr_l a18 input 2.5 v cmos write strobe: active low write strobe upx_rd_l h14 input 2.5 v cmos read strobe: active low read strobe upx_rdy_l c22 open drain output* 2.5 v cmos 1 cycle complete indicator: indicates that read or write is complete. note: an external pull-up resistor is required for proper operation. note: *dual-mode i/o. normal operation: open drain output boundary scan mode: standard cmos output table 6. pause control interface signal descriptions signal name ball designator type standard signal description txpausefr j7 input 2.5 v cmos pause strobe: indicates when a pause frame is to be sent txpauseadd3 txpauseadd2 txpauseadd1 txpauseadd0 k1 j2 g2 g3 input 2.5 v cmos pause address bus: selects the port for the pause frames table 5. cpu interface signal descriptions (sheet 2 of 2) signal name ball designator type standard signal description 1. this i/o meets the 2.5 v cmos specification only during boundary scan mode.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 37 document number: 250210 revision number: 008 revision date: august 10, 2004 table 7. optical module interface signal descriptions (sheet 1 of 2) signal name ball designator type standard signal description tx_fault_0 tx_fault_1 tx_fault_2 tx_fault_3 tx_fault_4 tx_fault_5 tx_fault_6 tx_fault_7 tx_fault_8 tx_fault_9 m24 v23 y17 r15 w14 w11 w9 ac5 p8 l2 input 2.5 v cmos transmitter fault: input used to determine when there is a optical module transmitter fault. rx_los_0 rx_los_1 rx_los_2 rx_los_3 rx_los_4 rx_los_5 rx_los_6 rx_los_7 rx_los_8 rx_los_9 l22 v17 ad18 r12 ab15 v12 y9 ac3 t2 p2 input 2.5 v cmos receiver loss of signal: input used to determine when the optical module receiver loses synchronization. mod_def_0 mod_def_1 mod_def_2 mod_def_3 mod_def_4 mod_def_5 mod_def_6 mod_def_7 mod_def_8 mod_def_9 n24 y21 aa16 m20 ac14 u11 t4 ab2 r7 l1 input 2.5 v cmos module definition: input used to determine when a optical module module is present. tx_disable_0 tx_disable_1 tx_disable_2 tx_disable_3 tx_disable_4 tx_disable_5 tx_disable_6 tx_disable_7 tx_disable_8 tx_disable_9 k22 m22 ac22 u18 u14 aa18 u9 aa9 v7 l4 open drain output* 2.5 v cmos 1 transmitter disable: output used to disable a optical module transmitter. external pull-up resistor usually resident in a optical module is required for proper operation. note: *dual-mode i/o. normal operation: open drain output boundary scan mode: standard cmos output tx_fault_int b11 open drain output* 2.5 v cmos 1 transmitter fault interrupt: open drain output interrupt to signal a tx_fault condition. note: *dual-mode i/o. normal operation: open drain output boundary scan mode: standard cmos output 1. this i/o meets the 2.5 v cmos specification only during boundary scan mode.
intel ? ixf1110 10-port gigabit ethernet media access controller 38 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 rx_los_int b14 open drain output* 2.5 v cmos 1 receiver loss of signal interrupt: open drain output interrupt to signal an rx_los condition. note: *dual-mode i/o. normal operation: open drain output boundary scan mode: standard cmos output mod_def_int g15 open drain output* 2.5 v cmos 1 module definition interrupt: open drain output interrupt to signal a mod_def condition. note: *dual-mode i/o. normal operation: open drain output boundary scan mode: standard cmos output i 2 c_clk l19 output 2.5 v cmos i 2 c reference clock: clock used for i 2 c bus interface. i 2 c_data_0 i 2 c_data_1 i 2 c_data_2 i 2 c_data_3 i 2 c_data_4 i 2 c_data_5 i 2 c_data_6 i 2 c_data_7 i 2 c_data_8 i 2 c_data_9 g22 g23 j24 f22 e23 h24 g20 e22 g24 f24 input/ output* 2.5 v cmos 1 i 2 c data bus: data i/o for the i 2 c bus interface. note: *dual-mode i/o. normal operation: input/ output boundary scan mode: standard cmos output table 8. led interface signal descriptions signal name ball designator type standard signal description led_clk a19 output 2.5 v cmos led clock: clock output for the led block. led_data a20 output 2.5 v cmos led data: data output for the led block. led_latch k18 output 2.5 v cmos led latch: latch enable for the led block. table 7. optical module interface signal descriptions (sheet 2 of 2) signal name ball designator type standard signal description 1. this i/o meets the 2.5 v cmos specification only during boundary scan mode.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 39 document number: 250210 revision number: 008 revision date: august 10, 2004 table 9. jtag interface signal descriptions signal name ball designator type standard signal description tck aa24 input 2.5 v cmos jtag test clock: reference clock for jtag. tms t16 input 2.5 v cmos jtag test mode select: selects test mode for jtag. tdi ac18 input 2.5 v cmos jtag test data input: test data sampled with respect to the rising edge of tck. trst_l n18 input 2.5 v cmos jtag test reset: reset input for jtag test. tdo y24 output 2.5 v cmos jtag test data output: te st data driven with respect to the falling edge of tck. table 10. system interface signal descriptions signal name ball designator type standard signal description clk125 aa5 input 2.5 v cmos 125 mhz reference clock: input clock to pll. clk50 c21 input 2.5 v cmos spi4-2 reference clock: input clock to spi4-2 rx pll. input range is 40 mhz to 50 mhz. this clock multiplied by eight must equal the required rx spi4-2 data clock frequency. sys_res_l y4 input 2.5 v cmos system reset: system hard reset (active low).
intel ? ixf1110 10-port gigabit ethernet media access controller 40 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 11. power supply signal descriptions (sheet 1 of 2) signal name ball designator type standard signal description avdd1p8_1 d1 e24 ? ? 1.8 v analog power supply: 1.8 v supply for analog circuits. avdd1p8_2 p7 v14 p18 v18 v6 v11 ?? 1.8 v analog power supply: 1.8 v supply for analog circuits. avdd2p5_1 y1 ? ? 2.5 v analog power supply: 2.5 v supply for analog circuits. avdd2p5_2 n3 v10 n22 v15 p3 p22 ?? 2.5 v analog power supply: 2.5 v supply for analog circuits.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 41 document number: 250210 revision number: 008 revision date: august 10, 2004 vdd d6 d19 f21 j11 k5 l9 p9 r4 t11 w4 aa15 d10 d20 h10 j14 k8 l11 p11 r8 t14 w21 aa19 d11 e21 h15 k3 k17 l14 p14 r17 u10 aa6 ab4 d15 f4 j4 k4 k21 l16 p16 r21 u15 aa10 ?? 1.8 v digital power supply: 1.8 v core supply. vdd2 b4 b17 f8 h2 j12 m9 m19 n9 n19 u2 w8 aa2 ac12 b8 b21 f12 h6 j13 m12 m23 n12 n23 u6 w12 aa23 ac13 b12 d2 f13 h19 m2 m13 n2 n13 t12 u19 w13 ac4 ac17 b13 d23 f17 h23 m6 m16 n6 n16 t13 u23 w17 ac8 ac21 ?? 2.5 v digital power supply: 2.5 v i/o supply. gnd b6 c4 d12, d22 f6 f23 h12 j10 k2 k14 k23 l10 l24 m11 m21 n14 p10 p21 r2 r10 r19 t8 t17 t23 u12, u21 v16 w6 w19 y3 y15 aa3 aa12 aa21 ab17 ac7 ac19 b10 d4 d13 d24 f10 g10 h13 j15 k6 k16 k24 l12 m3 m14 n4 n17 p12 p23 r3 r11 r23 t9 t18 u4 u13 v2 w2 w7 w20 y8 y16 aa4 aa13 ab6 ab21 ac10 ac20 b15 d5 d17 e1 f15 h4 h17 j21 k9 k19 l3 l13 m4 m17 n8 n21 p13 p24 r6 r14 r24 t10 t19 u7 u16 v3 w3 w10 w23 y12 y18 aa7 aa14 ab7 ab23 ac11 ad21 b19 d8 d21 f2 f19 h8 h21 j23 k11 k20 l6 l15 m8 m18 n11 p1 p15 r1 r9 r16 t7 t15 t21 u8 u17 v13 w5 w15 y2 y13 aa1 aa8 aa17 ab10 ac6 ac15 ?? ground: ground return for all signals. table 11. power supply signal descriptions (sheet 2 of 2) signal name ball designator type standard signal description
intel ? ixf1110 10-port gigabit ethernet media access controller 42 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 12. unused balls/reserved signal name ball designator type standard signal description nc a5 g7 k7 m7 n20 p17 r13 t1 v8 w16 y11 aa22 ab18 ad4 ad8 a6 g8 l21 n1 p4 p19 r18 t6 v9 w18 y14 ab3 ab19 ad5 ad17 c10 h22 l23 n5 p5 p20 r20 u1 v19 y7 aa11 ab5 ab20 ad6 ad19 c15 j22 m1 n7 p6 r5 r22 v1 w1 y10 aa20 ab8 ab22 ad7 ad20 ? ? no connection. no ball a2 a24 b24 ab24 ac24 ad22 a3 b1 c1 ac1 ad1 ad23 a22 b2 c24 ac2 ad2 ad24 a23 b23 ab1 ac23 ad3 ?? balls removed from substrate. no pad a1 ? ? pad removed from substrate. use this ball location as a key for device placement onto the pcb.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 43 document number: 250210 revision number: 008 revision date: august 10, 2004 5.0 functional descriptions 5.1 media access controller 5.1.1 general description the intel ? ixf1110 main functional block consists of a 1000 mbps ethernet media access controller (mac), supporting the following features: 1000 mbps full-duplex operation independent enable/disable of any port detection of length erroror overly large packets rmon statistics and error counters cyclic redundancy check (crc) calculation and error detection programmable options: ? filter packets with errors ? filter, broadcast, multicast, and unicast address packets ? automatically pad transmitted packets less than the minimum frame size compliance with ieee 802.3x standard for flow control (symmetric pause capability) the mac is fully integrated, designed for use with ethernet 802.3 frame types, and is compliant with all of the required ieee 802.3 mac requirements. the mac adds preamble and start-of-frame delimiter (sfd) to all frames sent to it (transmit path) and removes preamble and sfd on all frames received by it (receive path). a crc check is also applied to all transmit and receive packets. packets with a bad crc are marked, counted in the statistics block, and may be optionally dropped or sent to the spi4-2 interface. 5.1.2 mac functions section 5.1.2.1, ?padding of undersized frames on transmit? on page 43 through section 5.1.2.3, ?filtering of receive packets? on page 44 cover the mac functions. 5.1.2.1 padding of undersized frames on transmit the padding feature allows ethernet frames smaller than 64 bytes to be transferred across the spi4-2 interface and automatically padded up to 64 bytes by the mac. this feature is enabled by setting bit 7 of the ?diverse config ($ port_index + 0x18)? on page 137 .
intel ? ixf1110 10-port gigabit ethernet media access controller 44 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 note: if frames under 64 bytes are sent to the mac, the padding feature must be enabled for proper operation. a 9-byte packet is the minimum size packet that can be padded up to 64 bytes. packets under 9 bytes are not padded and are automatically dropped. 5.1.2.2 automatic crc generation the automatic crc generation is used in conjunction with the padding feature to generate and append a correct crc to any incoming frame from the spi4-2 interface. this feature is enabled by setting bit 6 of the ?diverse config ($ port_index + 0x18)? on page 137 note: when padding of undersized frames on transmit is enabled, the automatic crc generation must be enabled for proper operation of the ixf1110. 5.1.2.3 filtering of receive packets this feature allows the mac to filter receive packets under various conditions and drop the packets via an interaction with the receive fifo control. note: jumbo frames (1519 - 9600 bytes) matching the filter conditions, which would cause the frame to be dropped by the rx fifo, are not dropped. instead, jumbo frames that are expected to be dropped by the rx fifo, based on the filter settings in table 74, ?rx packet filter control ($ port_index + 0x19)? on page 138 , are sent across the spi4-2 interface as an eop abort frame. jumbo frames matching the filter conditions are not counted in the rx fifo number of frames removed register because they are not removed by the rx fifo. only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in the table 74, ?rx packet filter control ($ port_index + 0x19)? on page 138 are actually dropped by the rx fifo and counted in the rx fifo number of frames removed. 5.1.2.3.1 filter on unicast packet match this feature is enabled when bit 0 of the rx packet filter control register = 1. any frame received in this mode containing a unicast destination address that does not match the station address is marked by the mac to be dropped. th e frame is dropped if the appropriate bit in the rx fifo errored frame drop enable register = 1. otherwise, all unicast frames are sent to the spi4-2 interface, but with an eop abort code to the switch or network processor. note: the vlan filter overrides the unicast filter. thus, a vlan frame cannot be filtered based on the unicast address. 5.1.2.3.2 filter on multicast packet match this feature is enabled when bit 1 of the rx packet filter control register = 1. any frame received in this mode containing a multicast destination address which does not match the port multicast address is marked by the mac to be dr opped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable register = 1. otherwise, all multicast frames are sent to the spi4-2 interface, but with an eop abort code to the switch or network processor.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 45 document number: 250210 revision number: 008 revision date: august 10, 2004 5.1.2.3.3 filter broadcast packets this feature is enabled when bit 2 of the ?rx packet filter control ($ port_index + 0x19)? = 1. any broadcast frame received in this mode is marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable register = 1. otherwise, all broadcast frames are sent to the spi4-2 interface, but with an eop abort code to the switch or network processor. 5.1.2.3.4 filter vlan packets this feature is enabled when bit 3 of the ?rx packet filter control ($ port_index + 0x19)? = 1. vlan frames received in this mode are marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable register = 1. otherwise, all vlan frames are sent to the spi4-2 interface, but with an eop abort code to the switch or network processor. 5.1.2.3.5 filter pause packets this feature is enabled when bit 4 of the ?rx packet filter control ($ port_index + 0x19)? = 0. pause frames received in this mode are marked by the mac to be dropped. the frame is dropped if the appropriate bit in the ?rx fifo errored frame drop enable ($ 0x59f)? = 1. otherwise, all pause frames are sent to the spi4-2 interface. 5.1.2.3.6 filter crc errored packets this feature is enabled when bit 5 of the ?rx packet filter control ($ port_index + 0x19)? = 0. frames received with an errored crc are marked as bad frames and may optionally be dropped in the rx fifo. otherwise, the frames are sent to the spi4-2 interface and may be dropped by the switch or system controller (see table 14, ?crc errored packets drop enable behavior? on page 46 ). note: when the crc error pass filter bit = 0 ( ?rx packet filter control ($ port_index + 0x19)? ), it takes precedence over the other filter bits. any packet (pause, unicast, multicast or broadcast packet) with a crc error will be marked as a bad frame when the crc error pass filter bit = 0. table 13. pause packets drop enable behavior pause frame pass frame drop en actions 10 packets are passed to the spi4-2 interface. they are not marked as bad and are sent to the switch or network processor. 00 packets are marked as bad but not dropped in the rx fifo. these packets are sent to the spi4-2 interface, but with an eop abort code to the switch or network processor. 11 packets are not marked as bad and sent to the switch or network processor, regardless of the frame drop en setting. 01 pause packets are marked as bad, are dropped in the rx fifo, and never appear at the spi4-2 interface.
intel ? ixf1110 10-port gigabit ethernet media access controller 46 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.1.3 flow control flow control is an ieee 802.3x-defined mechanism for one network node to request that its link partner take a temporary ?pause? in packet transmission. this allows the requesting network node to prevent fifo overruns and dropped packets, by managing incoming traffic to fit its available memory. the temporary pause allows the device to process packets already received or in transit, thus freeing up the fifo space allocated to those packets. the ixf1110 implements the ieee 802.3x standard rx fifo threshold-based flow control. when appropriately programmed, the mac can both generate and respond to ieee standard pause frames. the ixf1110 also supports externally triggered flow control through the transmit pause control interface. 5.1.3.1 802.3x flow control (full-duplex operation) the ieee 802.3x standard identifies four options related to system flow control: no pause symmetric pause (both directions) asymmetric pause (receive direction only) asymmetric pause (transmit direction only) the ixf1110 supports all four options on a per-port basis. bits 1:0 of the ?fc enable ($ port_index + 0x12)? on page 135 provide programmable control for enabling or disabling flow control in each direction independently. the ieee 802.3x flow control mechanism is accomplished within the mac sublayer, and is based on rx fifo thresholds called watermarks. the rx fifo level rises and falls as packets are received and processed. when the rx fifo reaches a watermark (either exceeding a high or dropping below a low after exceeding a high), the ixf1110 control sublayer signals an internal state machine to transmit a pause frame. the fifos automatically generate pause frames (also called control frames) to initiate the following: halt the link partner when the high watermark is reached. restart the link partner when the data stored in the fifo falls below the low watermark. figure 5 illustrates the ieee 802.3 fifo flow control functions. table 14. crc errored packets drop enable behavior crc errored pass frame drop en actions 10 packets are passed to the spi4-2 interface. they are not marked as bad and are sent to the switch or network processor. 00 packets are marked as bad but not dropped in the rx fifo. these packets are sent to the spi4-2 interface, but with an eop abort code to the switch or network processor. 11 packets are not marked as bad and are sent to the switch or network processor regardless of the frame drop en setting. 01 crc errored packets are marked as bad, dropped in the rx fifo, and never appear at the spi4-2 interface.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 47 document number: 250210 revision number: 008 revision date: august 10, 2004 5.1.3.1.1 pause frame format pause frames are mac control frames that are padded to the minimum size (64 bytes). figure 6 and figure 7 illustrate the frame format and contents. figure 5. packet buffering fifo mdi high water mark data flow mac transfer threshold * low water mark high water mark data flow low water mark rx fifo high txpausefr (external 802.3x pause frame generation strobe) tx fifo tx side mac rx fifo 802.3 flow control rx side mac spi4-2 interface figure 6. ethernet frame format b2277-01 da sa data fcs type/ length s f d preamble 61 4 6 6 2 46-1500 ethernet frame number of bytes note: 64 byte minimum / 1518 bytes maximum
intel ? ixf1110 10-port gigabit ethernet media access controller 48 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 an ieee 802.3 mac pause frame is identified by detecting all of the following: opcode of 00-01 length/type field of 88-08 da matching the unique multicast address (01-80-c2-00-00-01) xoff. a pause frame informs the link partner to halt transmission for a specified length of time. the pauselength octets specify the duration of the no-transmit period. if this time is greater than zero, the link partner must stop sending any further packets until this time has elapsed. this is referred to as xoff. xon. the mac continues to transmit pause frames with the specified pause length as long as the fifo level exceeds the threshold. if the fifo level falls below the threshold before the pause length time expires, the mac sends another pause frame with the pause length time specified as zero. this is referred to as xon and informs the link partner to resume normal transmission of packets. 5.1.3.1.2 pause settings the mac must send pause frames repeatedly to maintain the link partner in a pause state. the following two inter-related variables control this process: pause length is the amount of time, measured in multiples of 512 bit times, that the mac requests the link partner to halt transmission for. pause threshold is the amount of time, measured in multiples of 512 bit times, prior to the expiration of the pause length that the mac transmits another pause frame to maintain the link partner in the pause state. the transmitted pause length in the ixf1110 is set by the ?fc tx timer value ($ port_index + 0x07)" . the ixf1110 pause frame transmission interval is set by the ?pause threshold ($ port_index + 0x0e)? on page 134 . figure 7. pause frame format b3426-01 da* or 01-80- c2-00- 00-01 sa 88-08 fcs s f d preamble 61 4 662 pause opcode (00-01) pause length 22 46 pad (with 0s) 42 64 bytes number of bytes note: in the intel ? ixf1110 architecture, the tx block of the mac sets this as the pause multicast address. the rx interface of the mac will process this as the pause multicast or the mac address.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 49 document number: 250210 revision number: 008 revision date: august 10, 2004 5.1.3.1.3 response to received pause command frames when flow control is enabled in the receive direction (bit 0 in the ?fc enable ($ port_index + 0x12)? on page 135 ), the ixf1110 responds to pause command frames received from the link partner as follows: 1. the ixf1110 checks the entire frame to verify that it is a valid pause control frame addressed to the multicast address 01-80-c2-00 -00-01 (as specified in ieee 802.3, annex 31b) or has a destinations address matching the address programmed in the ?station address low ($ port_index + 0x00)" through ?station address high ($ port_index + 0x01)" . 2. if the pause frame is valid, the transmit side of the ixf1110 pauses for the required number of pause quanta, as specified in ieee 802.3, clause 31. 3. pause does not begin until completion of the frame currently being transmitted. the ixf1110 response to valid received pause frames is independent of the pause frame filter settings. refer to section 5.1.2.3.5, ?filter pause packets? on page 45 for additional details. 5.1.3.1.4 transmit pause control interface the transmit pause control interface allows an external device to trigger the generation of pause frames. the transmit pause control interface is completely asynchronous. it consists of four address signals (txpauseadd[3:0]) and a strobe signal (txpausefr). the required address for this interface operation is placed on the txpauseadd[3:0] signals and the txpausefr is pulsed high and returned low. refer to figure 8, ?transmit pause control interface? on page 50 and table 41, ?transmit pause control interface parameters? on page 112 . table 15 shows the valid decodes for the txpauseadd[3:0] signals. figure 8 illustrates the transmit pause control interface. note: flow control must be enabled in the ?fc enable ($ port_index + 0x12)? for transmit pause control interface operation. note: there are two additional decodes provided that allow the user to generate either an xoff frame or xon frame from all ports simultaneously. the default pause quanta for each port is held by the ?fc tx timer value ($ port_index + 0x07)" ). the default value of this register is 0x05e after reset is applied. table 15. valid decodes for txpauseadd[3:0] txpauseadd[3:0] tx pause control interface operation 0x0 transmits a pause frame on every port with a pause_time = zero (xon) (cancels all previous pause commands). 0x1 transmits a pause frame on port 0 with pause_time equal to the value programmed in the port 0 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0x2 transmits a pause frame on port 1 with pause_time equal to the value programmed in the port 1 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0x3 transmits a pause frame on port 2 with pause_time equal to the value programmed in the port 2 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0x4 transmits a pause frame on port 3 with pause_time equal to the value programmed in the port 3 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0x5 transmits a pause frame on port 4 with pause_time equal to the value programmed in the port 4 ?fc tx timer value ($ port_index + 0x07)" (xoff).
intel ? ixf1110 10-port gigabit ethernet media access controller 50 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.1.4 fiber operation the data path in the mac is an internal 10-bit interface, as described in the ieee 802.3z standard. it is connected directly to an internal serdes block for serialization/deserialization and transmission/reception on the fiber medium to/from the link partner. 0x6 transmits a pause frame on port 5 with pause_time equal to the value programmed in the port 5 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0x7 transmits a pause frame on port 6 with pause_time equal to the value programmed in the port 6 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0x8 transmits a pause frame on port 7 with pause_time equal to the value programmed in the port 7 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0x9 transmits a pause frame on port 8 with pause_time equal to the value programmed in the port 8 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0xa transmits a pause frame on port 9 with pause_time equal to the value programmed in the port 9 ?fc tx timer value ($ port_index + 0x07)" (xoff). 0xb - 0xe reserved 0xf transmits a pause frame on every port with pause_time equal to the value programmed in the ?fc tx timer value ($ port_index + 0x07)" for each port (xoff). figure 8. transmit pause control interface table 15. valid decodes for txpauseadd[3:0] txpauseadd[3:0] tx pause control interface operation b3366-01 txpausefr txpauseadd0 txpauseadd1 txpauseadd2 this example shows the following conditions: strobe 1: port 0: transmit pause packet (xoff) strobe 2: all ports: transmit pause packet with pause_time = 0 (xon) strobe 3: port 3: transmit pause packet (xoff) txpauseadd3
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 51 document number: 250210 revision number: 008 revision date: august 10, 2004 note: the mac contains all the pcs (8b/10b encoding and 10b/8b decoding) required to encode and decode the data. the mac also supports auto-negotiation per the ieee 802.3z standard via access to the ?tx config word ($ port_index + 0x17)? on page 136 , ?rx config word ($ port_index + 0x16)? on page 135 , and diverse config registers (see ?diverse config ($ port_index + 0x18)? on page 137 . by default, ixf1110 auto-negotiation is disabled by register bit 5 (an_enable) of the ?diverse config ($ port_index + 0x18)? . when auto-negotiation is disabled, the ixf1110 can operate in forced mode, which is 1000 mbps full duplex only. this is equivalent to entering the state an_disable_link_ok as described in figure 37-6 of ieee 802.3. the ixf1110 can pass packets when auto-negotiation is disabled only when the internal synchronization state machine indicates that the sync_status is ok as described in figure 36-9 of ieee 802.3. note: packet ipg must contain a minimum of three consecutive /i1/ or /i2/ ordered sets per ieee 802.3 for correct operation. note: the ixf1110 treats the k28.1 code word as an unknown control word; therefore, it should not be used. 5.1.5 auto-negotiation auto-negotiation is carried out by an internal state machine within the mac in the ixf1110. the ixf1110 is fully ieee 802.3z standard compliant. the following three registers are involved in this auto-negotiation process: rx config word tx config word, and diverse config: the ?rx config word ($ port_index + 0x16)? performs the operation of auto-negotiation base page ability. the ?tx config word ($ port_index + 0x17)? performs the operation of auto-negotiation advertisement. the ?diverse config ($ port_index + 0x18)? enables auto-negotiation. the ?tx config word ($ port_index + 0x17)? must be written to program the modes advertised. the ?diverse config ($ port_index + 0x18)? bit 5 (an_enable) must be written to enable auto- negotiation. the ?rx config word ($ port_index + 0x16)? bit 21 (an_complete) must be polled to determine when auto-negotiation is complete. the following mac registers must be programmed to match the results upon completion: link led: table 80, ?link led enable ($ 0x502)? on page 149 flow control: if the link partner does not support flow control, the ?fc enable ($ port_index + 0x12)? on page 135 must be updated to reflect this change. note: in auto-negotiation mode, the tx spi4-2 status bus (tstat[1:0]) is held in the satisfied state until auto-negotiation completes and a valid link is established. this prevents the tx fifo from being filled prior to transmission of packets. 5.1.5.1 determining if link is established in auto-negotiation mode a valid link is established when the (an_complete) bit is set and the rx_sync bit reports synchronization has occurred. both register bits are located in the ?rx config word ($ port_index + 0x16)? .
intel ? ixf1110 10-port gigabit ethernet media access controller 52 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 if the link goes down after auto-negotiation is completed, rx_sync indicates that a loss of synchronization occurred. the ixf1110 restarts auto-negotiation and attempts to re-establish a link. once a link has been re-established, the an_complete bit is set and the rx_sync bit shows that synchronization has occurred. to manually restart auto-negotiation, bit 5 of the ?diverse config ($ port_index + 0x18)? (an_enable) must be de-asserted, then re-asserted. 5.1.6 forced mode operation the fiber operation of the mac can be forced to operated at 1000 mbps, full duplex without completion of the auto negotiation function. in this mode, the receive path of the mac must achieve synchronization with the link partner. once this has been achieved, the transmit path of the mac will be enabled to allow data transmission, which is known as ?forced mode? operation. forced mode is limited to operation with a link partner that operates with a full-duplex link at a speed of 1000 mbps. forced mode is enabled by register bit 5 (an_enable) in the ?diverse config ($ port_index + 0x18)? . by default, the ixf1110 is set to forced mode operation. note: in forced mode, the tx spi4-2 status bus (tstat[1:0]) is held in the satisfied state until sync_status is ok. this prevents the tx fifo from being filled prior to transmission of packets. 5.1.6.1 determining if link is established in forced mode when the ixf1110 is in forced mode operation, the ?rx config word ($ port_index + 0x16)? bit 20 rx sync indicates when synchronization has occurred and valid link is established. note: the rx sync bit indicates a loss of synchronization when the link is down. 5.1.7 jumbo packet support the ixf1110 supports the concept of jumbo frames. the jumbo frame length is dependent on the application, and the ixf1110 design has been optimized for 9.6 kb jumbo frame length. lengths larger than this can be programmed, but will limit system performance. the value programmed into the max frame size register (addr: port_index + 0x0f) determines the maximum length frame size the mac can receive or transmit without activating any error counters, and without truncation. the max frame size register (addr: port_index + 0x0f) bits 13:0 set the frame length. the default value programmed into this register is 0x05ee (1518). the value is internally adjusted by +4 if the frame has a vlan tag. the overall programmable maximum is 0x3fff or 16383 bytes. the register should be programmed to 0x2667 for the 9.6 kb length jumbo frame for which the ixf1110 is optimized. the rmon counters are also affected for jumbo frame support as follows: rx statistics: rxoctetstotalok (addr: port_index + 0x20) rxpkts1519tomaxoctets (addr: port_index + 0x2b)
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 53 document number: 250210 revision number: 008 revision date: august 10, 2004 rxfcserrors (addr: port_index + 0x2c) rxdataerror (addr: port_index + 0x02e) rxalignerrors (addr: port_index + 0x2f) rxlongerrors (addr: port_index + 0x30) rxjabbererrors (addr: port_index + 0x31) rxverylongerrors (addr: port_index + 0x34) tx statistics: txoctetstotalok (addr: port_index + 0x40) txpkts1519tomaxoctets (addr: port_index + 0x4b) txexcessivelengthdrop (addr: port_index + 0x53) txcrcerror (addr: port_index + 0x56) the ixf1110 checks the crc for all legal length jumbo frames (frames between 1519 and the max frame size). on transmission, the mac can be programmed to append the crc to the frame or check the crc and increment the appropriate counter. on reception, the mac transmits these frames across the spi4-2 interface (jumbo frames with a bad crc cannot be dropped and are sent across the spi4-2 interface). if the receive frame has a bad crc, the appropriate counter is incremented and the eop abort code is set in the spi4-2 control word. jumbo frames also impact flow control. the maximum frame size needs to be taken into account when determining the fifo watermarks. the current transmission must be completed before a pause frame can be transmitted (needed when the receiver fifo high watermark has been exceeded). if the current transmission is a jumbo frame, the delay may be significant and increase data loss due to insufficient available fifo space. 5.1.8 rmon statistics support 5.1.8.1 rmon statistics the ixf1110 supplies rmon statistics via the cpu interface. these statistics are available in the form of counter values that can be accessed at specific addresses in the ixf1110 memory map. once read, these counters automatically reset and begin counting from zero. a separate set of rmon statistics is available for each mac device in the ixf1110. implementation of the rmon statistics block is similar to the functionality provided by existing intel switch and router products. this implementation allows the ixf1110 to provide all of the rmon statistics group as defined by rfc2819. the ixf1110 supports the rmon rfc2819 group 1 statistics counters. table 16 notes the differences and additional statistics registers supported by the ixf1110 that are outside the scope of the rmon rfc2819 document.
intel ? ixf1110 10-port gigabit ethernet media access controller 54 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 16. rmon additional statistics registers (sheet 1 of 2) rmon ethernet statistics group 1 statistics type ixf1110 equivalent statistics type definition of rmon versus ixf1110 documentation etherstatsindex integer32 n/a n/a n/a etherstatsdatasource object identifier n/a n/a n/a etherstatsdropevents counter32 rx/tx fifo number of frames removed counter32 see table note 1. etherstatsoctets counter32 rxoctetstotalok rxoctetsbad txoctetstotalok txoctetsbad counter32 note: the ixf1110 has two counters for rx and tx that use different naming conventions for total octets and octets bad. these counters need to be combined to meet the rmon spec. etherstatspkts counter32 rx/txucpkts rx/txbcpkts rx/txmcpkts counter32 note: the ixf1110 has three counters for etherstatspkts that need to be combined to give the total packets as defined by the rmon spec. etherstatsbroadcastpkts counter32 rx/txbcpkts counter32 ok etherstatsmulticastpkts counter32 rx/txmcpkts counter32 see table note 2. etherstatscrcalignerrors counter32 rxalignerrors rxfcserrors txcrcerror counter32 note: the ixf1110 has two counters for alignment and crc errors for the rx side only. the ixf1110 has crcerror for the tx side. etherstatsoversizepkts counter32 rxlongerrors txexcessivelengthdrop counter32 ok etherstatsjabbers counter32 rxjabbererrors counter32 ok 1. the rmon spec requires that this is, "the total number of events where packets were dropped by the probe due to a lack of resources. note that this number is not necessarily the number of packets dropped; it is the number of times this condition has been detected." the rx/tx fifo number of frames removed register in the ixf1110 supports this and will increment when either an rx or tx fifo has over flowed. if any ixf1110 programmable packet filtering is enabled, the rx/tx number of frames removed register increments with every frame removed in addition to the existing frames counted due to fifo overflow. 2. the ixf1110 has an extra counter rx/txucpkts that can be used. 3. the ixf1110 has an extra counter rx/txpktstomaxoctets that can be used in addition to the rmon stats. this is required to accommodate the jumbo packet frames requirement.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 55 document number: 250210 revision number: 008 revision date: august 10, 2004 5.1.8.2 conventions the following conventions are used throughout the rmon mib and its companion documents. good packets : error-free packets that have a valid frame length. for example, on ethernet, good packets are error-free packets that are between 64 octets long and 1518 octets long. they follow the form defined in ieee 802.3, section 3.2. bad packets : packets that have proper framing and are therefore recognized as packets, but contain errors within the packet or have an invalid length. for example, on ethernet, bad packets have a valid preamble and sfd, but have a bad crc, or are either shorter than 64 octets or longer than 1518 octets. 5.1.8.3 additional statistics the following additional ixf1110 registers support features not documented in rmon: mac (flow) control frames vlan tagged frames etherstatscollisions counter32 txsinglecollisions txmultiplecollisions txlatecollisions txtotalcollisions counter32 ok note: registers exist on the tx side but should not increment since the ixf1110 only supports full- duplex. etherstatspkts64octets counter32 rx/txpkts64octets counter32 ok etherstatspkts65to127octets counter32 rx/txpkts65to127octets counter32 ok etherstatspkts128to255octets counter32 rx/txpkts128to255octets counter32 ok etherstatspkts256to511octets counter32 rx/txpkts256to511octets counter32 ok etherstatspkts512to1023octets counter32 rx/txpkts512to1023octets counter32 ok etherstatspkts1024to1518octet s counter32 rx/ txpkts1024to1518octets counter32 see table note 3. etherstatsowner owner string n/a n/a n/a etherstatsstatus entry status n/a n/a n/a table 16. rmon additional statistics registers (sheet 2 of 2) rmon ethernet statistics group 1 statistics type ixf1110 equivalent statistics type definition of rmon versus ixf1110 documentation 1. the rmon spec requires that this is, "the total number of events where packets were dropped by the probe due to a lack of resources. note that this number is not necessarily the number of packets dropped; it is the number of times this condition has been detected." the rx/tx fifo number of frames removed register in the ixf1110 supports this and will increment when either an rx or tx fifo has over flowed. if any ixf1110 programmable packet filtering is enabled, the rx/tx number of frames removed register increments with every frame removed in addition to the existing frames counted due to fifo overflow. 2. the ixf1110 has an extra counter rx/txucpkts that can be used. 3. the ixf1110 has an extra counter rx/txpktstomaxoctets that can be used in addition to the rmon stats. this is required to accommodate the jumbo packet frames requirement.
intel ? ixf1110 10-port gigabit ethernet media access controller 56 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 sequence errors symbol errors crc errors these additional counters allow for additional differentiation over and above standard rmon probes. note: a packet transfer with an invalid 10-bit symbol will not always update the statistics registers correctly. behavior: the ixf1110 8b10b decoder substitutes a valid code word octet in its place. the packet transfer is aborted and marked as bad. the new internal length of the packet is equal to the byte position where the invalid symbol was. no packet fragments are seen at the next packet transfer. issue: if the invalid 10-bit code is inserted in a byte position of 64 or greater, expected rx statistics are reported. however, if the invalid code is inserted in a byte position of less than 64, expected rx statistics are not stored.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 57 document number: 250210 revision number: 008 revision date: august 10, 2004 5.2 system packet interface level 4 phase 2 the system packet interface level 4 phase 2 (spi4-2) provides a high-speed connection to a network processor or an asic. the interface implemented on the ixf1110 operates at data rates up to 12.8 gbps and supports up to ten 1 gbps mac ports. the data path is 16 lanes wide in each direction, with each lane operating from 640 mbps up to 800 mbps. port addressing, start/end packet control, and error control codes are all transferred ?in-band? on the data bus. in-band addressing supports up to 10 ports. separate transmit and receive fifo status lines are used for flow control. by keeping the fifo status information out-of-band, the transmit and receive interfaces may be de-coupled to operate independently. figure 9 and table 17 provide an overview of the ixf1110 spi4-2 interface. figure 9. spi4-2 interfacing with the network processor or forwarding engine table 17. spi4-2 interface signal summary (sheet 1 of 2) signal name signal description transmit tdat[15:0]_p/n transmit data bus: differential lvds lines used to carry payload data and in-band control words. internally terminated differentially with 100 ?. tdclk_p/n transmit data clock: differential lvds clock associated with tdat[15:0] and tctl. data and control lines are driven off the rising and falling edges of the clock. internally terminated differentially with 100 ?. note: if tdclk is applied to the ixf1110 after the device has come out of reset, the system designer must ensure the tdclk is stable when applied. failure to due so can result in the ixf1110 training on a non-stable clock, causing dip4 errors and data corruption. tctl_p/n transmit control: differential lvds lines used to indicate when a control word is being transmitted. a high level indicates a control word present on tdat[15:0]. internally terminated differentially with 100 ?. intel ? ixf1110 mac network processor or forwarding engine with spi4-2 interface tsclk tsclk tdat[15:0]_p/n spi-4.2 signals tstat[1:0] tstat[1:0] tdat[15:0]_p/n tdclk_p/n tdclk_p/n tctl_p/n tctl_p/n rsclk rsclk rstat[1:0] rstat[1:0] rdclk_p/n rdclk_p/n rdat[15:0]_p/n rdat[15:0]_p/n rctl_p/n rctl_p/n transmit fifo status/ flow control receive fifo status/ flow control transmit data control receive data control b3432-01
intel ? ixf1110 10-port gigabit ethernet media access controller 58 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.2.1 data path transfer of complete packets or shorter bursts is controlled by the programmed maxburst1 or maxburst2 in conjunction with the fifo status bus. the maximum configured payload data transfer size must be a multiple of 16 bytes. control words are inserted between burst transfers only. once a transfer begins, data words are sent uninterrupted until an end-of-packet, or until a multiple of 16 bytes is reached as programmed in maxburst1 and maxburst2. the interval between the end of a given transfer and the next payload control word (marking the start of another transfer) consists of zero or more idle control words and/or training patterns. note: the system designer should be aware that the mac transfer threshold register must be set to a value which exceeds the maxburst1 setting of the network processor or asic. otherwise, a tx fifo under-run may result. the minimum and maximum supported packet lengths are determined by the application. because the ixf1110 is targeted at the ethernet environment, the minimum frame size is 64 bytes and the maximum frame size is 1522 bytes for vlan packets (1518 bytes for non-vlan packets). for larger frames, adjust the value of the ?max frame size ($ port_index + 0x0f)? on page 134 . for ease of implementation, successive start-of-packets must occur not less than eight cycles apart, where a cycle is one control or data word. the gap between shorter packets is filled with idle control words. note: data packets with frame lengths less than 64 bytes should not be transferred to the ixf1110 unless packet padding is enabled. if this rule is disregarded, unwanted fragments may be generated on the network at the serdes interface. figure 10 on page 59 shows cycle-by-cycle behavior of the data path for valid state transitions. the states correspond to the type of words transferred on the data path. transitions from the ?data burst? state (to ?payload control? or ?idle control?) are possible only on the integer multiples of tsclk transmit status clock: lvttl clock associated with tstat [1:0]. frequency is equal to one-quarter tdclk. tstat1, tstat0 transmit fifo status: lvttl lines used to carry round-robin fifo status information, along with associated error detection and framing. receive rdat[15:0]_p/n receive data: carries payload data and in-band control from the ixf1110 link-layer device. internally terminated differentially with 100 ? rdclk_p/n receive data clock: differential lvds clock associated with rdat[15:0] and rctl. data and control lines are driven off the rising and falling edges of the clock. internally terminated differentially with 100 ? rctl_p/n receive control: rctl is high when a control word is present on rdat[15:0]. otherwise, rctl is low. internally terminated differentially with 100 ? rsclk receive status clock: lvttl clock associated with rstat[1:0]. rstat1, rstat0 receive fifo status: lvttl lines used to carry round-robin fifo status information, along with associated error detection and framing. table 17. spi4-2 interface signal summary (sheet 2 of 2) signal name signal description
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 59 document number: 250210 revision number: 008 revision date: august 10, 2004 eight cycles (corresponding to multiples of 16-byte segmentations) or upon end-of-packet. a data burst must immediately follow a payload control word on the next cycle. arcs not annotated correspond to single cycles. in the ixf1110, the rx fifo status channel operates in a ?pessimistic mode.? it is termed as pessimistic because it has the longest latency and largest impact on usable bandwidth. however, as a dip-2 check error is a rare event, there will be no ?real world? effect on bandwidth utilization and no possibility of data loss. for example, if there is a dip-2 check error found, all previously granted credits are cancelled and the internal status for each port is set to satisfied. any current data burst in transmission is completed. no new credits are granted until a complete fifo status cycle has been received and validated by a correct dip-2 check. this is the only method of operation that can eliminate the possibility of an overrun in the link partner device. 5.2.1.1 control words a common control word format is used in both the transmit and receive interfaces. table 18 describes the fields in the control word. when inserted in the data path, the control word is aligned such that its msb is sent on the msb of the transmit or receive data lines. a payload control word that separates two adjacent burst transfers contains status information pertaining to the previous transfer and the following transfer. table 19 provides a list of control-word definitions. figure 10. data path state
intel ? ixf1110 10-port gigabit ethernet media access controller 60 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 18. control word format bit position label description 15 type control word type. set to either of the following values: 0 = idle or training control word 1 = payload control word (payload transfer will immediately follow the control word) 14:13 eops end-of-packet (eop) status. set to the following values according to the status of the immediately preceding payload transfer: 00 =not an eop. 01 = eop abort (application-specific error condition 10 =eop normal termination, 2 bytes valid 11 = eop normal termination, 1 byte valid eops is valid in the first control word following a burst transfer. it is ignored and set to ?00? otherwise. 12 sop start-of-packet. set to 1 if the payload transfer immediately following the control word corresponds to the start of a packet. set to 0 otherwise. set to 0 in all idle and training control words 11:4 adr port address. 8-bit port address of the payload data transfer immediately following the control word. none of the addresses are reserved (all are available for payload transfer). set to all zeroes in all idle control words set to all ones in all training control words 3:0 dip-4 4-bit diagonal interleaved parity. 4-bit odd parity computed over the current control word and the immediately preceding data words (if any) following the last control word table 19. control word definitions (sheet 1 of 2) bit [15:12] next word status prior word status meaning 0 0000 idle continued idle, not eop, training control word 1 0001 reserved reserved reserved 2 0010 idle eop w/abort idle, abort last packet 3 0011 reserved reserved reserved 4 0100 idle eop w/ 2 bytes idle, eop with 2 bytes valid 5 0101 reserved reserved reserved 6 0110 idle eop w/ 1 byte idle, eop with 1byte valid 7 0111 reserved reserved reserved 8 1000 valid none valid, no sop, no eop 9 1001 valid/sop none valid, sop, no eop a 1010 valid eop w/abort valid, no sop, abort b 1011 valid/sop eop w/abort valid, sop, abort c 1100 valid eop w/ 2 bytes valid, no sop, eop with 2 bytes valid
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 61 document number: 250210 revision number: 008 revision date: august 10, 2004 the spi4-2 specification details all available payload control words and should be used to reference the specific meaning of each. the ixf1110 supports all required functions per this specification. however, there are various specifics in the way certain control words affect the balance of the ixf1110 operation, such as how the device deals with eop aborts. the spi4-2 specification allows the eop abort payload control word, which signals that the data associated with a particular frame is errored and should be dropped, or errored and dropped by the far-end link partner. in the ixf1110, all tx spi4-2 transfers that end with an eop abort code have the tx serdes crc corrupted. this is true regardless of the mac configuration. figure 11 shows per-port state transitions at control-word boundaries. at any given time, a port may be active (sending data), paused (not sending data but pending the completion of an outstanding packet), or inactive (not sending data, no outstanding packet). 5.2.1.2 eop abort eop aborts is an end-of-packet (eop) termination that is sent out of the ixf1110 spi4-2 to tell the upstream spi4-2 device that a packet is bad. eop abort packets are sent by the ixf1110 under the following conditions: d 1101 valid eop w/ 2 bytes valid, sop, eop with 2 bytes valid e 1110 valid eop w/ 1 byte valid, no sop, eop with 1byte valid f 1111 valid eop w/ 1 byte valid, sop, eop with 1byte valid table 19. control word definitions (sheet 2 of 2) bit [15:12] next word status prior word status meaning figure 11. per-port state diagram with transitions at control words port [ n ] inactive port [ n ] active port [ n ] paused pc[ n ] & -sop (ic i pc[- n ]) & -eop pc[ n ] & eop & sop pc[ n ] & sop (ic i pc[- n ]) & eop pc[ n ] & -eop & -sop key: ic: idle control word pc[ n ]: payload control word for port n pc[- n ): payload control word for a port other than port n sop: start-of-packet in payload control word -sop: no start-of-packet in payload control word eop: end-of-:acket in control word -eop: no end-of-packet in control word &: and i: or
intel ? ixf1110 10-port gigabit ethernet media access controller 62 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 standard size (64-1518 byte) packets that are filtered ( ?rx packet filter control ($ port_index + 0x19)? ) but not dropped due to the setting in the ?rx fifo errored frame drop enable ($ 0x59f)? (see section 5.1.2.3, ?filtering of receive packets? on page 44 ). standard size (64-1518 byte) packets that are greater in size than the setting in the ?max frame size ($ port_index + 0x0f)? and are not dropped due to the setting in the ?rx fifo errored frame drop enable ($ 0x59f)? . jumbo frames that meet the filter conditions set in the ?rx packet filter control ($ port_index + 0x19)? on page 138 or are above the ?max frame size ($ port_index + 0x0f)? on page 134 . rx fifo overflows. packets received with /v/ error codes on the serdes interface that are not dropped due to settings in the ?rx fifo errored frame drop enable ($ 0x59f)? on page 159 . runt packets (under 64 bytes) received that are not dropped due to the setting in the ?rx fifo errored frame drop enable ($ 0x59f)? on page 159 . note: eop abort packets sent out on the rx spi4-2 may have the packet size modified. when an eop abort packet is received on the tx spi4-2, the ixf1110 sends the packet out to the serdes interface with an invalid crc and is recorded in the tx statistics as a crc error. 5.2.1.3 dip4 figure 12 shows the range over which the diagonal interleaved parity (dip-4) parity bits are computed. a functional description of calculating the dip-4 code is given as follows. assume that the stream of 16-bit data words are arranged as shown in figure 13 (msb at the left most column, time moving downward). (the first word received is at the top of the figure; the last word is at the bottom of the figure.) the parity bits are generated by summing diagonally (in the control word, the space occupied by the dip-4 code (bits a, b, c, d) is set to all 1s during encoding). the first 16- bit result is split into two bytes, which are added to each other modulo-2 to produce an 8-bit result. the 8-bit result is then divided into two 4-bit nibbles, which are added to each other modulo-2 to produce the final dip-4 code. the procedure described applies to either parity generation on the rx path or to check parity on the tx path. figure 12. dip-4 calculation boundaries a9039-01 payload payload dip-4 codewords control control control control
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 63 document number: 250210 revision number: 008 revision date: august 10, 2004 5.2.2 start-up parameters 5.2.2.1 calendar_len calendar_len specifies the length of each calendar sequence. as the ixf1110 is a 10-port device, calendar_len is fixed at 10 for both tx and rx data paths. figure 13. dip-4 calculation algorithm a9040-01 1st spi-4 phase ii data word of incoming burst 10 101 01 100 01 011 1 10 10101 0 11 10101 0 01 00000 0 16-bit parity sum (dip16[15:0]) 01 00 00 00 01 00 dip4 parity bits (dip4[3:0]) 8-bit parity sum dip4[3] = dip16[15] dip16[11] dip16[7] dip16[3] dip4[2] = dip16[14] dip16[10] dip16[6] dip16[2] dip4[1] = dip16[13] dip16[9] dip16[5] dip16[1] dip4[0] = dip16[12] dip16[8] dip16[4] dip16[0] a, b, c and d are all set to 1 during encoding. 0 321 control word: not included in parity calculations below 2nd spi-4 phase ii data word of incoming burst 3rd spi-4 phase ii data word of incoming burst 4th spi-4 phase ii data word of incoming burst 5th spi-4 phase ii data word of incoming burst 6th spi-4 phase ii data word of incoming burst 7th spi-4 phase ii data word of incoming burst 8th spi-4 phase ii data word of incoming burst 10 110 10 111 00 010 0 00 001 10 100 10 011 0 00 110 00 001 00 000 0 11 010 11 111 10 000 0 00 000 00 001 00 010 0 00 010 10 111 00 000 0 11 010 10 100 01 011 0 10 110 00 000 00 000 0 11 110 0a 0bc 00 010 d 0 321 4 765 8 11 10 9 12 15 14 13 to 2 to 3 to 4 to 5 to 6 to 7 to 8 to 9 2 3 4 5 6 7 8 9 00 100 1w 1xy 00 010 z each bit of this 16-bit parity sum is the result of a xor operation along the corresponding dashed line. control word: included in parity calculations (contains the results of parity for the 8 spi-4 phase ii data words above and this control word)
intel ? ixf1110 10-port gigabit ethernet media access controller 64 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.2.2.2 calendar_m calendar_m specifies the number of times the calendar port status sequence is repeated between the framing and dip2 cycle of the calendar sequence. in the ixf1110, the tx path calendar_m is fixed at 1; thus, the port status for ports 0 - 9 will be transmitted only once between the framing and dip2 cycle of the calendar sequence. in the ixf1110, the rx path calendar_m is also fixed at 1. thus, the status for port 0-9 must only be sent once between framing and dip2. therefore, the value of both tx and rx calendar_m parameters is always fixed a 1. 5.2.2.3 dip2_thr dip2_thr is a parameter specifying the number of consecutive correct dip2s required by the rx spi4-2 to validate a calendar sequence and therefore terminate sending training sequences. in table 103, ?spi4-2 rx calendar ($ 0x702)? on page 173 , bits 19 to 16 specify this parameter. the default value for dip2_thr is 1. 5.2.2.4 loss_of_sync loss_of_sync is a parameter specifying the number of consecutive framing calendar cycles required to indicate a loss of synchronization and therefore restart training sequences. table 103, ?spi4-2 rx calendar ($ 0x702)? on page 173 , bits 11 to 8 specify this parameter. the default value for loss_of_sync is three. 5.2.2.5 data_max_t data_max_t is an rx spi4-2 parameter specifying the interval between transmission of periodic training sequences. in table 102, ?spi4-2 rx training ($ 0x701)? on page 172 , bits 15 to 0 specify this parameter. the default value for data_max_t is 0x0000, which disables periodic training sequence transmission. 5.2.2.6 rep_t rep_t is an rx spi4-2 parameter specifying the number of repetitions of the training sequence to be scheduled every data_max_t interval. in table 102, ?spi4-2 rx training ($ 0x701)? on page 172 , bits 23 to 16 specify this parameter. the default value for rep_t is 0x00. 5.2.2.7 dip4_unlock dip4_unlock is a tx spi4-2 parameter specifying the number of consecutive incorrect dip4 fields to be detected in order to declare loss of synchronization and drive tstat[1:0] bus with framing. in table 104, ?spi4-2 tx synchronization ($ 0x703)? on page 174 , bits 15 to 8 specify this parameter. the default value for dip4_unlock is 0x4. 5.2.2.8 dip4_lock dip4_lock is a tx spi4-2 parameter specifying the number of consecutive correct dip4 fields to be detected in order to declare synchronization achieved and enable the calendar sequence. in
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 65 document number: 250210 revision number: 008 revision date: august 10, 2004 table 104, ?spi4-2 tx synchronization ($ 0x703)? on page 174 , bits 7 to 0 specify this parameter. the default value for dip4_lock is 0x20. 5.2.2.9 maxburst1 maxburst1 is an rx spi4-2 parameter specifying the maximum number of 16 byte blocks that may be transmitted when the associated fifo status indicates ?starving?. bits 24 to 16 of the spi4-2 rx burst size register specify this parameter. the default value for maxburst1 is 0x006, indicating a maxburst1 of 96 bytes [see table 101, ?spi4-2 rx burst size ($ 0x700)? on page 172 ]. 5.2.2.10 maxburst2 maxburst2 is an rx spi4-2 parameter specifying the maximum number of 16 byte blocks that may be transmitted when the associated fifo status indicates ?hungry?. bits 8 to 0 of the spi4-2 rx burst size register specify this parameter. the default value for maxburst2 is 0x002, indicat- ing a maxburst2 of 32 bytes (see table 101, ?spi4-2 rx burst size ($ 0x700)? on page 172 ). 5.2.3 dynamic phase alignment training sequence (data path de-skew) 5.2.3.1 training at start-up the spi4-2 specification states that on power-up or after a reset, the training sequence (as defined in the spi4-2 specification) is sent indefinitely by the source side until it receives valid fifo status on the fifo bus. the specification also states that it is possible for the bus de-skew to be completed after one training sequence takes place. it is unlikely that the bus can be de-skewed in a single training sequence because of the presence of both random and deterministic jitter. the only way to account for the random element is to determine an average over repeated training sequences. since the required number of repeats is dependent on several characteristics of the system in which the ixf1110 is being used, power on training (or training following loss of synchronization) will continue until synchronization is achieved and the calendar is provisioned. the length of power on training will not be a fixed number of repeats. the number of training sequence repeats could be fairly large (16, 32, or 64). if this is necessary every time training is required, a significant use of interface bandwidth is needed just to train and de-skew the data path. this is only done at power-up or reset for an optimal starting point interface. after this, periodic training provides a better adjustment and a substantially lower bandwidth overhead. 5.2.3.2 periodic training a scheduled training sequence is sent at least once every pre-configured bounded interval (data_max_t) on both the transmit and receive paths. these training sequences are used by the receiving end of each interface for de-skewing bit arrival times on the data and control lines. the sequence allows the receiving end to correct for relative skew difference of up to +/- 1 bit time. the training sequence consists of one (1) idle control word followed by one or more repetitions of a 20- word training pattern consisting of 10 (repeated) training-control words followed by 10 (repeated) training-data words.
intel ? ixf1110 10-port gigabit ethernet media access controller 66 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 the initial idle control word removes dependencies of the dip-4 in the training control words from preceding data words. assuming a maximum of +/- bit time alignment jitter on each line, and a maximum of +/- bit time relative skew between lines, there are at least eight bit times when a receiver can detect a training control word prior to de-skew. the training data word is chosen to be orthogonal to the training control word. in the absence of bit errors in the training pattern, a receiver should be able successfully to de-skew the data and control lines with one training pattern. the sending side of the data path on both the transmit and receive interfaces must schedule the training sequence at least once every data_max_t cycles. note: data_max_t may be set to zero, disabling periodic training on the interface (refer to table 102, ?spi4-2 rx training ($ 0x701)? on page 172 ). this is done when a system shows very little drift during normal operation, and no fine-grain correction on an on-going basis is needed. this allows the maximum possible bandwidth for data transfer. the transmit and receive interface training sequences are scheduled independently. 5.2.3.3 training in a practical implementation the oif standard states that it should be possible to train and de-skew the data input in a single training cycle. however, from the research carried out and the variances in jitter and skew due to board layout and clock tolerance issues, some sort of averaging over several repeated training patterns is required to reliably determine the optimal point at which to capture the incoming data. this is true for both static alignment and dynamic phase alignment. therefore, several training patterns are required for an average. the more training patterns, the more accurate the average. the de-skew circuit in the ixf1110 uses dynamic phase alignment with a typical averaging requirement of 32 training patterns required to deliver a reliable result. during power-on training, an unlimited number of training cycles is sent by the data sourcing device. (the standard states that training must be sourced until a calendar has been provisioned.) in the ixf1110, the de-skew circuit waits until completion of its programmed average over the training patterns, ensuring that the required number of good dip-4s is seen. only then is a calendar provisioned. during periodic training, it is important to ensure that the training result is no less accurate than that already used for the initial decision during power-on training. thus, a similar number of training cycles must be averaged over (32). this could make the overhead associated with periodic training large if it is required to be carried out too often. we therefore recommend that periodic training be scheduled infrequently (data_max_t = a large number) and that the number of repetitions of training be = 32( ). 5.2.4 fifo status channel fifo status information is sent periodically over the tstat link from the ixf1110 to the upper layer processor device, and over the rstat link from the upper layer processor to the ixf1110. the status channels operate independently. figure 14 shows the operation of the fifo status channel. the sending side of the fifo status channel is initially in the disable state and sends the ?1 1? pattern repeatedly. when fifo status transmission is enabled, there is a transition to the sync state and the ?1 1? framing pattern is sent. fifo status words are then sent according to the calendar sequence, repeating the sequence calendar_m times, followed by the dip-2 code.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 67 document number: 250210 revision number: 008 revision date: august 10, 2004 the fifo status of each port is encoded in a 2-bit data structure, which is defined in table 20, ?fifo status format? on page 69 . the most significant bit of each port status is sent over tstat[1]/rstat[1] and the least significant bit is sent over tstat[0]/rstat[0]. the ?1 1? pattern is reserved for in-band framing, which must be sent once prior to the start of the fifo status sequence. immediately before the ?1 1? framing pattern, a dip-2 odd parity checksum is sent at the end of each complete sequence. the dip-2 code is computed diagonally over tstat[1]/rstat[1] and tstat[0]/rstat[0] for all preceding fifo status indications sent after the last ?1 1? framing pattern, as shown in figure 15, ?example of dip-2 encoding? on page 68 . the first word is at the top of the figure and the last word is at the bottom. the parity bits are computed by summing diagonally. bits a and b in line 9 correspond to the space occupied by the dip-2 parity bits and are set to 1 during encoding. the ?1 1? framing pattern is not included in the parity calculation. the procedure described applies to either parity generation on the egress path or to check parity on the ingress path. figure 14. fifo status state diagram port 4 po rt 3 po rt 2 por t 1 por t 0 port 9 po rt 8 po rt 7 por t 6 por t 5 sync 11 di p- 2 en a b l e dis a b le 11 di s a b l e
intel ? ixf1110 10-port gigabit ethernet media access controller 68 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 when the parity bits mimic the ?1 1? pattern, the receiving end still frames successfully by syncing onto the last cycle in a repeated ?1 1? pattern, and by making use of the configured sequence length when searching for the framing pattern. to permit more efficient fifo utilization, the maxburst1 and maxburst2 credits are granted and consumed in increments of 16-byte blocks. for any given port, these credits correspond to the most recently received fifo status. they are not cumulative and supersede previously granted credits for the given port. a burst transfer shorter than 16 bytes (for example, an end-of-packet fragment) consumes an entire 16-byte credit. a continuous stream of repeated ?1 1? framing patterns indicates a disabled status link. for example, it may be sent to indicate that the data path de-skew is not yet completed or confirmed. when a repeated ?1 1? pattern is detected, all outstanding credits are cancelled and set to zero. figure 15. example of dip-2 encoding dip2 parity bits framing pattern (not included parity in calculations) 1st status word 2nd status word 3rd status word 4th status word 5th status word 6th status word 7th status word 8th status word dip2 parity bits (dip2[1:0]) a and b are set to 1 during enccoding 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 a b 2 3 4 5 6 7 8 9 to 2 to 3 to 4 to 5 to 6 to 7 to 8 to 9 1 0
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 69 document number: 250210 revision number: 008 revision date: august 10, 2004 the indicated fifo status is based on the latest available information. a starving indication provides additional feedback information, so that transfers are scheduled accordingly. applications that do not distinguish between hungry and starving may only examine the most significant fifo status bit. note: if a port is disabled on the ixf1110, fifo status for the port is set to satisfied to avoid the possibility of any data being sent to it by the controlling device. this applies to the ixf1110 transmit path. upon reset, the fifos in the data path receiver are emptied, and any outstanding credits are cleared in the data path transmitter. after reset, and before active traffic is generated, the data transmitter sends continuous training patterns. transmission of the training patterns continues until valid information is received on the fifo status channel. the receiver ignores all incoming data until it has observed the training pattern and acquired synchronization with the data. synchronization may be declared after a provisional number of consecutive correct dip-4 code words is seen. loss of synchronization may be reported after a provisional number of consecutive dip-4 code words is detected. [for details, see table 104, ?spi4-2 tx synchronization ($ 0x703)? on page 174 .] the dip-4 thresholds are programmable. however, there is a potential issue with the possibility of a given link showing dip-4 errors that may never lose synchronization and re-train to fix the issue. this would mean an on-going and potentially significant loss of data on the link affecting all ports transferring data at that time. this issue may be seen in the following two instances: during training (most likely periodic training) during data transfers where each of the data transfers (maxburst1 or maxburst2) are separated by more than one idle control word table 20. fifo status format msb lsb description 1 1 reserved for framing or to indicate a disabled status link. 10 satisfied: indicates that the corresponding port's fifo is almost full. when satisfied is received, only transfers using the remaining previously granted 16-byte blocks (if any) may be sent to the corresponding port until the next status update. no additional transfers to that port are permitted while satisfied is indicated. 01 hungry: when hungry is received, transfers for up to maxburst2 16-byte blocks, or the remainder of what was previously granted (whatever is greater), may be sent to the corresponding port until the next status update. 00 starving: indicates that buffer underflow is imminent in the corresponding phy port. when starving is received, transfers for up to maxburst1 16-byte blocks may be sent to the corresponding port until the next status update
intel ? ixf1110 10-port gigabit ethernet media access controller 70 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 the mechanism for both issues is the same because data will not change during a repeated period of the same control word being transmitted on the link. if there have been some consecutive dip-4 errors, they will be incremented towards the loss-of-sync threshold. this is most likely to occur from a path requiring de-skew. if either a stream of idles or training control words follow the burst and the dip-4 associated with each of the words is checked, only the first one and the last one will be seen as invalid. any other control words in the middle will be seen as having a valid dip-4 and will reset the loss-of-sync threshold counter back to zero. in order to avoid this, the ixf1110 has altered the way in which the check is done for idle control words and training control words. we now only validate the first occurrence of the dip-4 in both training control words and idle control words for correctness. we do still check each of the words but only use the first occurrence to clear the dip-4 error counter. any dip-4 error in any of these words is still counted towards the loss-of-sync threshold counter. it is now impossible to mask the dip-4 error on our interface. 5.2.5 dc parameters for dc parameters on the spi4-2 interface, please refer to table 36, ?2.5 v lvttl and cmos i/ o electrical characteristics? on page 107 and table 37, ?lvds i/o electrical characteristics? on page 107 . 5.3 serdes interface 5.3.1 introduction the ixf1110 has ten integrated serializer/deserializer (serdes) devices that allow direct connection to optical modules. each serdes interface is fully compliant with the relevant ieee 802.3 specifications, including auto-negotiation (see ?fiber operation? on page 50 . each port is also compliant with and supports the requirements of the small form factor pluggable (sfp) multi-source agreement (msa), see ?optical module interface? on page 72 . the following sections describe the operations supported by each serdes interface, the configurable options, and register bits that control these options. (a full list of the register addresses and full bit definitions are found in the register map ( table 58, ?serdes block register map? on page 130 ). 5.3.2 features the serdes cores are designed to operate in point-to-point data transmission applications. while the core can be used across various media types, such as pcb or backplanes, it is configured specifically for use in 1000base-x ethernet fiber applications in the ixf1110. the following features are supported. 10-bit data path, which connects to the output/input of the 8b/10b encoder/decoder pcs that resides in the mac controller data frequency of 1.25 ghz low power: <200 mw per serdes port asynchronous clock data recovery
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 71 document number: 250210 revision number: 008 revision date: august 10, 2004 5.3.3 functional description the serdes transmit interface sends serialized data at 1.25 ghz. the interface is differential with two pins for transmit operation. the transmit interface is designed to operate in a 100 ? differential environment and all the terminations are included on the device. the outputs are high speed serdes and ac coupling is recommended for this interface to ensure that the correct input bias current is supplied at the receiver. the serdes receive interface receives serialized data at 1.25 ghz. the interface is differential with two pins for the receive operation. the equalizer receives a differential signal that is equalized for the assumed media channel. the serdes transmit and receive interfaces are designed to operate within a 100 ? differential environment and all terminations are included on the device. 5.3.3.1 transmitter operational overview the transmit section of the ixf1110 has to serialize the ten bit interface (tbi) data from the ixf1110 mac section and outputs this data at 1.25 ghz differential signal levels. the 1.25 ghz differential serdes signals are compliant with the small form factor pluggable (sfp) multi- source agreement (msa). the transmitter section takes the contents of the data register within the mac and synchronously transfers the data out, ten bits at a time ? least significant bit (lsb) first, followed by the next most significant bit (msb). when these ten bits have been serialized and transmitted, the next word of 10-bit data from the mac is ready to be serialized for transmission. the data is transmitted by the high-speed current mode differential serdes output stage using an internal 1.25 ghz clock generated from the 125 mhz clock input. 5.3.3.2 transmitter programmable driver-power levels the ixf1110 serdes core has programmable transmitter power levels to enhance usability in any given application.the serdes registers are programmable to allow adjustment of the transmit core driver output power. when driving a 100 ? differential terminated network, these output power set- tings effectively establish the differential voltage swings at the driver output. the (register) allows the selection of 4 discrete power settings. the selected power setting of these inputs is applied to each of the transmit cores drivers on a per-port basis. table 17, ?spi4-2 interface signal summary? lists the normalized power setting of the transmit drivers as a function of the driver power control inputs. the normalized current setting is 10 ma which corresponds to the nor- malized power setting of 1.0. this is the default setting of the ixf1110 serdes interface. other val- ues listed in the normalized driver power setting column are multiples of 10 ma. for example, with inputs at 1110, the driver power is .5 x 10 ma = 5 ma. table 21. serdes driver tx power levels drvpwrx[3] drvpwrx[2] drvpwrx[1] drvpwrx[0] normalized driver power setting driver power 0 0 1 1 1.33 13.3 ma 1011 2.0 20 ma 1101 1.0 10 ma 1110 0.5 5 ma note: all other values are reserved.
intel ? ixf1110 10-port gigabit ethernet media access controller 72 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.3.3.3 receiver operational overview the receiver structure performs clock and data recovery (cdr) on the incoming serial data stream. the quality of this operation is a dominant factor for the bit error rate (ber) system performance. feed forward and feedback controls are combined in one receiver architecture for enhanced performance. the data is over-sampled and a digital circuit detects the edge position in the data stream. a signal is not generated if an edge is not found. a feedback loop takes care of low-frequency jitter phenomenon of unlimited amplitude, while a feed forward section suppresses high-frequency jitter having limited amplitude. the static edge position is held at a constant position in the over-sampled by a constant adjustment of the sampling phases with the early and late signals. 5.3.3.4 selective power-down the ixf1110 offers the ability to selectively power-down any of the serdes tx or rx ports that are not being used. this is done via ?serdes tx and rx power-down ports 0-9 ($ 0x787)? on page 175 . 5.3.4 timing and electrical characteristics for timing and electrical characteristics for the ixf1110, see figure 39, ?serdes timing? on page 118 , ?transmitter characteristics? on page 118 and ?receiver characteristics? on page 119 . 5.4 optical module interface 5.4.1 introduction this section describes the connection of the ixf1110 ports to an optical module, and the connections supported for correct operation are detailed. the registers used to write control and read status information are documented in section 8.5.9, ?optical module interface block register overview? on page 176 ). the optical module interface allows the ixf1110 a seamless connection to the small form factor optical modules (sfp) that form the system?s physical media connection, eliminating the need for any fpgas or cpus to process data. all required information of the optical modules is available to the system cpu through the ixf1110 cpu interface, leading to a more integrated, reliable, and cost-effective system. 5.4.2 ixf1110 supported optical module interface signals. for optical module interface operation, three supported signal subgroups are required, allowing a more explicit definition of each function and implementation. the three subgroups are as follows: high-speed serial interface low-speed status signaling interface i 2 c module configuration interface table 22 provides descriptions for ixf1110- to-sfp optical module connection pins.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 73 document number: 250210 revision number: 008 revision date: august 10, 2004 5.4.3 functional descriptions 5.4.3.1 high-speed serial interface these signals are responsible for transfer of the actual data at 1.25 gbps. the data is 8b/10b encoded and transmitted differentially at serdes levels per the required specifications. the signals required to implement the high-speed serial interface are: tx_9:0_p tx_9:0_n rx_9:0_p rx_9:0_n 5.4.3.2 low-speed status signaling interface the following low-speed signals indicate the state of the line via the optical module: mod_def_9:0 tx_fault_9:0 rx_los_9:0 tx_disable_9:0 mod_def_int tx_fault_int rx_los_int table 22. ixf1110-to-sfp connections ixf1110 pin names sfp module pin name description notes tx_9:0_p td+ transmit data, differential serdes output from the ixf1110 tx_9:0_n td- rx_9:0_p rd+ receive data, differential serdes input to the ixf1110 rx_9:0_n rd- i 2 c_clk mod-def1 i 2 c_clk output from ixf1110 (scl) output from the ixf1110 i 2 c_data_9:0 mod-def2 i 2 c_data i/o (sda) input/output mod_def_9:0 mod-def0 mod_def(0) should be ttl low level during normal operation. input to the ixf1110 tx_disable_9:0 tx disable transmitter disable, logic high, open collector compatible output from the ixf1110 tx_fault_9:0 tx fault transmitter fault, logic high, open collector compatible input to the ixf1110 rx_los_9:0 los receiver loss of signal, logic high, open collector compatible input to the ixf1110
intel ? ixf1110 10-port gigabit ethernet media access controller 74 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.4.3.2.1 mod_def_9:0 these signals are direct inputs to the ixf1110 and are pulled to a logic low level during normal operation, indicating that a module is present for each port, respectively. if a module is not present, a logic high is received, which is achieved by an external pull-up resistor at the ixf1110 pad. the status of each bit (one for each port) is found in bits 9:0 of the optical module status register (refer to table 108, ?optical module status ports 0-9 ($ 0x799)? on page 176 ). any change in the state of these bits causes a logic low level on the mod_def_int output if this operation is enabled. 5.4.3.2.2 tx_fault_9:0 these 10 pins are inputs to the ixf1110. these signals are pulled to a logic low level by the optical module during normal operation, which indicates no fault condition exists. if a fault is present, a logic high is received via the use of an external pull-up resistor at the ixf1110 pad. the status of each bit (one for each port) can be found in bits 19:10 of the optical module status register (see table 108, ?optical module status ports 0-9 ($ 0x799)? on page 176 ). any change in the state of these bits causes a logic low level on the tx_fault_int output if this operation is enabled. 5.4.3.2.3 rx_los_9:0 these 10 pins are inputs to the ixf1110. during normal operation, these signals are pulled to a logic low level by the optical module, which indicates that no loss-of-signal exists. if a loss-of- signal occurs, a logic high is received on these inputs via the use of an external pull-up resistor at the ixf1110 pad. the status of each bit (one for each port) is found in ?optical module status ports 0-9 ($ 0x799)? bits 29:20. any change in the state of these bits causes a logic low level on the rx_los_int output if this operation is enabled. 5.4.3.2.4 tx_disable_0:9 these 10 pins are outputs from the ixf1110. during normal operation, these signals are pulled to a logic low level by the ixf1110, indicating that the optical module transmitter is enabled. if the optical module transmitter is disabled, these signals are switched to a logic high level. on the ixf1110, these outputs are open-drain types and pulled up by the 4.7k to 10k pull-up resistor at the optical module. each of these signals is controlled via ?optical module control ports 0-9 ($ 0x79a)? bits 9:0, respectively. 5.4.3.2.5 mod_def_int mod_def_int is a single output, open-drain type signal, and is active low. a change in state of any of the mod_def_9:0 inputs causes this signal to switch low and remain in this state until a read of the ?optical module status ports 0-9 ($ 0x799)? takes place. the signal then returns to an inactive state.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 75 document number: 250210 revision number: 008 revision date: august 10, 2004 note: the mod_def_9:0 inputs shown in table 108, ?optical module status ports 0-9 ($ 0x799)? on page 176 are synchronized with an internal system clock. this results in a delay from the time the signal is active to the register bit and/or interrupt being set. 5.4.3.2.6 tx_fault_int tx_fault_int is a single output, open-drain type signal, and is active low. a change in state of any of the tx_fault_9:0 inputs causes this signal to switch low and remain in this state until a read of the ?optical module status ports 0-9 ($ 0x799)? takes place. the signal then returns to an inactive state. note: the tx_fault_9:0 inputs shown in table 108, ?optical module status ports 0-9 ($ 0x799)? on page 176 are synchronized with an internal system clock. this results in a delay from the time the signal is active to the register bit and/or interrupt being set. 5.4.3.2.7 rx_los_int rx_los_int is a single output, open-drain type signal, and is active low. a change in state of any of the rx_los_0:9 inputs causes this signal to switch low and remain in this state until a read of the optical module status register has taken place. the signal then returns to an inactive state. note: the rx_los_0:9 inputs shown in table 108, ?optical module status ports 0-9 ($ 0x799)? on page 176 are synchronized with an internal system clock. this results in a delay from the time the signal is active to the register bit and/or interrupt being set. note: mod_def_int, tx_fault_int, and rx_los_int are open-drain type outputs. with the three signals on the device, the system can decide which optical module status register bits to look at to identify the interrupt condition source port. however, this is achieved at the expense of two device pins. in systems that cannot support multiple interrupt signals (applications that do not have extra hardware pins), these three outputs can be connected to a single pull-up resistor and used as a single interrupt pin. 5.4.4 i 2 c module configuration interface the i 2 c interface is supported on sfp optical modules. details of the operation are found in the sfp multi-source agreement (msa). this document details the contents of the registers and addresses accessible on a given optical module supporting this interface. the sfp msa identifies up to 512 8-bit registers that are accessible in each optical module. the i 2 c interface is read/write capable and supports either sequential or random access to the 8-bit parameters. the maximum clock rate of the interface is 100 khz. all address select pins on the internal e 2 prom are tied low to give a device address equal to zero (00h). the specific interface in the ixf1110 supports only a subset of the full i 2 c interface, and only the features required to support the optical modules are implemented, leading to the following support features: single i 2 c_clk pin connected to all modules, and implemented to save unnecessary pin use. ten per-port i 2 c_data pins optical (i 2 c_data_9:0) are required due to the optical module requirement that all modules must be addressed as 00h.
intel ? ixf1110 10-port gigabit ethernet media access controller 76 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 due to the single internal controller, only one optical module may be accessed at any one time. optical module accesses contains a single register read. since these register accesses will most likely be done during power-up or discovery of a new module, these restrictions should not affect normal operation. the i 2 c interface also supports byte write accesses to the full address range. 5.4.4.1 general description in the ixf1110, the entire i 2 c interface is controlled through separate i 2 c control and data registers (see ?i2c control ports 0-9 ($ 0x79b)? on page 176 and ?i2c data ports 0-9 ($ 0x79c)? on page 177 . the general operation is described below. the i 2 c control register is divided into the following sections: port address error write protect error bit no acknowledge error bit i 2 c enable bit i 2 c start access bit write access complete bit read datavalid bit 4-bit port address select read/write access select 4-bit device id 11-bit register address the i 2 c data register is divided into the following sections: 8-bit write data 8-bit read data the 4-bit device id field defaults to ah, this value is compatible with standard fiber module based on the atmel serial e 2 prom family. i 2 c accesses to non-atmel compatible devices will require to update this field with the appropriate value. the 11-bit register address is split into two sub-fields: bits [10:8] must be set to 0h to be compatible with standard fiber optical module. alternatively these bits can be set to 1h - 7h to permit access to seven other i 2 c component on the same bus. bits [7:0] specify the particular location to be accessed within the device specified by the device id field and register address[10:8]. initiating an access where the 4-bit port address field to a value > 9h will not generate an i 2 c access. instead the port address error will be set. initiating a write access where the device id field = ah and the register address[10:8] = 0h will generate an i 2 c access. in addition the write protect error bit will be set to indicate a write has been initiated to the write protected optical module.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 77 document number: 250210 revision number: 008 revision date: august 10, 2004 5.4.4.1.1 read access operation example the following sequence provides an example of reading the data stored in the optical module register 0x000 for port 5: 1. program the ?i2c control ports 0-9 ($ 0x79b)? on page 176 with the following information: a. enable i 2 c block by setting bit 25 to ?1?. b. set the port to be accessed by setting bits [19:16] to 0x5. c. select a read access by setting bit 15 to ?1?. d. set the device id, bits [14:11] to be 0xa (atmel compatible). e. set the 11-bit register address, bits [10:0] to 0x000. f. initiate the i 2 c transfer by setting bit 24 to ?1?. all other bits in this register should be written with the value ?0?. this data is written into the i 2 c control register in a single cycle via the cpu interface. 2. when this register is written and the i 2 c start bit is at a logic 1, the i 2 c access state machine examines the port address select and enables the i 2 c_data_0:9 output for the selected port. 3. the state machine uses the data in the device id and register address fields to build the data frame to be sent to the optical module. 4. the i 2 c data_read_fsm internal state machine takes over the task of transferring the actual data between the ixf1110 and the selected optical module (refer to the details in section 5.4.4.2, ?i2c protocol specifics? on page 78 ). 5. the i 2 c data_read_fsm internal state machine places the received data into the read_data field, bits [7:0] of the i 2 c data register, and sets the read data valid bit, bit 20 of the i 2 c control register to ?1? to signify that the read data is valid. 6. the data is read through the cpu interface. the cpu must poll the read data valid bit until it is set to ?1. only once this bit is set, it is safe to read the data in the i 2 c data register. 5.4.4.1.2 write access operation example the following sequence provides an example of writing data to the optical module register 0xff for port 9: 1. program the ?i2c control ports 0-9 ($ 0x79b)? with the following information: a. enable i 2 c block by setting bit 25 to ?1?. b. set the port to be accessed by setting bits [19:16] to 0x9. c. select a write access by setting bit 15 to ?0?. d. set the device id, bits [14:11] to be 0xa (atmel compatible). e. set the 11-bit register address, bits [10:0] to 0xff. f. initiate the i 2 c transfer by setting bit 24 to ?1?. all other bits in this register should be written with the value ?0?. this data is written into the i 2 c control register in a single cycle via the cpu interface.
intel ? ixf1110 10-port gigabit ethernet media access controller 78 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 2. when this register is written and the i 2 c start bit is at a logic 1, the i 2 c access state machine examines the port address select and enables the i 2 c_data_0:9 output for the selected port. 3. the state machine uses the data in the device id and register address fields to build the data frame to be sent to the optical module. 4. the i 2 c data_write_fsm internal state machine takes over the task of transferring the actual data between the ixf1110 and the selected optical module (refer to the details in section 5.4.4.2, ?i2c protocol specifics? on page 78 ). 5. the i 2 c data_write_fsm internal state machine uses the data from the write_data field, bits [23:16] of the i 2 c data register, and sets the write_complete bit, bit 22 of the i 2 c control register to ?1? to signify that the write access is complete. 6. the data is written through the cpu interface. the cpu must poll the write_complete bit until it is set to ?1. only once this bit is set, it is safe to request a new access. note: only one optical module i 2 c access sequence can be run at any given time. if a second write is carried out to the i 2 c control register before a result is returned for the previous write, the data for the first write is lost. to ensure no data is lost, make sure write complete = 1 before starting the next write sequence. 5.4.4.2 i 2 c protocol specifics this section describes the i 2 c protocol behavior supported by the ixf1110, which is controlled by an internal state machine. specific protocol states are defined below, with an additional description of the hardware pins used on the interface. the serial clock line (i 2 c_clk) is an ixf1110 output. the serial data is synchronous with this clock and is driven off the rising edge by the ixf1110 and off the falling edge by the optical module. the ixf1110 has only one i 2 c_clk line that drives all of the optical modules. the i 2 c_clk runs continuously when enabled (i 2 c enable = 01h0). the serial data (i 2 c_data_0:9) pins (one per port) are bi-directional for serial data transfer, and are open drain. 5.4.4.3 port protocol operation 5.4.4.4 clock and data transitions the i 2 c_data is normally pulled high with an extra device. data on the i 2 c_data pin changes only during the i 2 c_clk low time periods (see figure 16 ). data changes during i 2 c_clk high periods indicate a start or stop condition.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 79 document number: 250210 revision number: 008 revision date: august 10, 2004 5.4.4.4.1 start condition a high-to-low transition of i 2 c_data, with i 2 c_clk high, is a start condition that must precede any other command (see figure 17 ). 5.4.4.4.2 stop condition a low-to-high transition of the i 2 c_data with i 2 c_clk high is a stop condition. after a read sequence, the stop command places the e 2 prom in the optical in a standby power mode (see figure 17 ). 5.4.4.4.3 acknowledge all addresses and data words are serially transmitted to and from the optical module in 8-bit words. the optical module e 2 prom sends a zero to acknowledge that it has received each word, which happens during the ninth clock cycle (see figure 18 ). figure 16. data validity timing data stable data stable data change i 2 c_data i 2 c_clk figure 17. start and stop definition timing start stop i 2 c_data i 2 c_clk
intel ? ixf1110 10-port gigabit ethernet media access controller 80 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.4.4.4.4 memory reset after an interruption in protocol, power loss, or system reset, any two-wire optical module can be reset by following three steps: 1. clock up to nine cycles 2. wait for i 2 c_data high in each cycle while i 2 c_clk is high 3. initiate a start condition the following defines device memory reset: always add a stop condition following the start as there is no clean finish to end the reset of the memory with a start condition after completing steps one through three. this ensures a clean protocol termination if there is no more data to transfer at the end of the reset cycle. 5.4.4.4.5 device addressing all e 2 proms in optical module devices require an 8-bit device address word following a start condition to enable the chip to read or write. the device address word consists of a mandatory one, zero sequence for the four most significant bits. this is common to all devices. the next 3 bits are the a2, a1 and a0 device address bits that are tied to zero in a optical module. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon comparison of the device address, the optical module outputs a zero. if a comparison is not made, the optical module e 2 prom returns to a standby state. when not accessing the optical module e 2 prom, the device address or device id is completely programmable for maximum flexibility. 5.4.4.4.6 random read operation a random read requires a ?dummy? byte/write sequence to load the data word address. the following describes how to achieve the ?dummy? write: figure 18. acknowledge timing start acknowledge i 2 c_data data in data out
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 81 document number: 250210 revision number: 008 revision date: august 10, 2004 the ixf1110 generates a start condition. the ixf1110 sends a device address word with the read/write bit cleared to low, signaling a write operation. the optical module acknowledges receipt of the device address word. the ixf1110 sends the data word address, which is again acknowledged by the optical module. the ixf1110 generates another start condition. this completes the ?dummy? write and sets the optical module e 2 prom pointers to the desired location. the following describes how the ixf1110 initiates a current address read: the ixf1110 sends a device address with the read/write bit set high the optical module acknowledges the device address and serially clocks out the data word. the ixf1110 does not respond with a zero but generates a stop condition (see figure 19 ). timing diagrams and tables can be found in section 7.0, ?electrical specifications? on page 105 . 5.4.4.4.7 byte write operation the following describes how to achieve the byte write operation: the ixf1110 generates a start condition. the ixf1110 sends a device address word with the read/write bit cleared to low, signaling a write operation. the optical module acknowledges receipt of the device address word. the ixf1110 sends the data word address. the optical module acknowledges receipt of the data word address. the ixf1110 sends the data byte to be written. the optical module acknowledges the data word. the ixf1110 generates a stop condition (see figure 20 ). figure 19. random read device address device address word address sda line dummy write (* = don't care bit for 1k) start s t a r t r e a d s t a r t w r i t e s t o p m s b m s b m s b l s b r / w l s b data n l s b a c k n o a c k a c k
intel ? ixf1110 10-port gigabit ethernet media access controller 82 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.4.4.5 ac timing characteristics table 43, ?i2c ac timing characteristics? on page 114 , figure 35, ?i2c bus timing? on page 114 , and figure 36, ?i2c write cycle? on page 114 provide the ac timing characteristics of the optical module interface. 5.5 led interface 5.5.1 introduction the ixf1110 uses a serial interface consisting of three signals to provide led data to a serial-to- parallel logic external driver. the three signals are as follows: led clk: this clock is provided by the ixf1110 to clock the external parallel-to-serial shift registers. led data: this serial data is provided by the ixf1110 to the external parallel-to-serial shift registers. led latch: this latch is provided by the ixf1110 to latch the data on the parallel-to-serial shift registers. the led_data stream provides data for 30 separate direct drive leds and allows three leds per mac port. the three led pins outlined above are detailed in table 23, ?led signal descriptions? . there are two modes of operation, each with its own separate led decode mapping. modes of operation and leds are detailed in section 5.5.2, ?modes of operation? . 5.5.2 modes of operation mode selection is accomplished by using bit 0 of the ?led control ($ 0x509)? on page 151 . this bit is globally selected and controls the mode of operation of all ports section 5.5.2.1 and section 5.5.2.2 provide the two modes of operation. figure 20. byte write device address word address i 2 c_data line (* = don't care bit for 1k) s t a r t w r i t e m s b m s b l s b r / w l s b a c k * a c k s t o p data n a c k a c k
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 83 document number: 250210 revision number: 008 revision date: august 10, 2004 5.5.2.1 mode 0 this mode selects operations compatible with the sgs thompson m5450 led display driver device. this device converts the serial data stream, output by ixf1110, into 30 direct-drive led outputs. in this mode, the latch signal is not required. this mode is selected by setting bit 0 of the ?led control ($ 0x509)? to 0 (default). 5.5.2.2 mode 1 this mode selects operations compatible with ttl (74ls595) or hcmos (74hc595) octal shift registers. this device converts the serial data stream, output by ixf1110, into 30 direct-drive led outputs. in this mode the led data, led clk and led latch signals are used. this mode is selected by setting bit 0 of the ?led control ($ 0x509)? to 1. 5.5.3 led interface signal description the ixf1110 led interface consists of three output signal pins that are 2.5 v cmos level pads. table 23, ?led signal descriptions? provides led signal names, pin numbers, and descriptions. 5.5.4 mode 0: detailed operation note: please refer to the sgs thompson m5450 datasheet for device-operation information. the operation of the led interface in mode 0 is based on a 36-bit counter loop. the data for each led is placed in turn on the serial data line and clocked out by the led_clk. figure 21 on page 84 shows the basic timing relationship and relative positioning in the data stream of each bit. figure 21 shows the 36 clocks that are output on the led_clk pin. the data changes on the falling edge of the clock and is valid for almost the entire clock cycle. this ensures that the data is valid during the rising edge of the led_clk, which is used to clock the data into the m5450 device.the actual data shown in figure 21 consists of a chain of 36 bits only, 30 of which are valid led data. the 36-bit data chain is built up as follows: table 23. led signal descriptions signal name ball designator signal description led_clk a20 led_clk: this signal is an output that provides a continuous clock synchronous to the serial data stream output on the led_data pin. this clock has a maximum speed of 720 hz. the behavior of this signal remains constant in all modes of operation. led_data a19 led_data: this signal provides the data, in various formats, as a serial bit stream. the data must be valid on the rising edge of the led_clk signal. in mode 0, the data presented on this pin is true (logic 1 = high). in mode 1, the data presented on this pin is inverted (logic 1 = low). led_latch k18 led_latch: this is an output pin and the signal is used only in mode 1 as the latch enable for the shift register chain. this signal is not used in mode 0, and should be left unconnected.
intel ? ixf1110 10-port gigabit ethernet media access controller 84 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 when implemented on a board with the m5450 device, the led data bit 1 appears on output bit 3 of the m5450 and the led data bit 2 appears on output bit 4, etc. this means that output bits 1, 2, 3, 34, and 35 will never have valid data and should not be used. 5.5.5 mode 1: detailed operation note: please refer to manufacturers? 74ls/hc595 datasheet for information on device operation. the operation of the led interface in mode 1 is again based on a 36-bit counter loop. the data for each led is placed in turn on the serial data line and clocked out by the led_clk. figure 22 on page 85 shows the basic timing relationship and relative positioning in the data stream of each bit. figure 22 shows the 36 clocks that are output on the led_clk pin. the data changes on the falling edge of the clock and is valid for almost the entire clock cycle. this ensures that the data is valid during the rising edge of the led_clk, which is used to clock the data into the shift register chain devices. the led_latch signal is required in mode 1, and is used to latch the data shifted into the shift register chain into the output latches of the 74hc595 device. as seen in figure 22 , the led_latch signal is active high during the low period on the 36th led_clk cycle. this avoids any possibility of trying to latch data as it is shifting through the register. figure 21. mode 0 timing table 24. mode 0 clock cycle to data bit relationship led_clk cycle led_data name led_data description 1start bit this bit is used to synchronize the m5450 device to expect 35 bits of data to follow. 2:3 pad bits these bits are used only as fillers in the data stream to extend the length from the actual 30 bit led data to the required 36-bit frame length. these bits should always be a logic 0. 4:33 led data 1-30 these bits are the actual data transmitted to the m5450 device. the decode for each individual bit in each mode is defined in table 23, ?led signal descriptions? on page 83 . the data is true. logic 1(led on) = high 34:36 pad bits these bits are used as fillers in the data stream to extend the length from the actual 30-bit led data to the required 36-bit frame length. these bits should always be a logic 0. 1 23 24 25 26 27 28 29 30 135 26 234 led_clk led_data led_latch 34 27 33 32 31 30 29 28 36
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 85 document number: 250210 revision number: 008 revision date: august 10, 2004 when this operation mode is implemented on a board with a shift register chain containing three 74hc595 devices, the led data bit 1 is output on shift register bit 1, and so on up the chain. only shift register bits 31 and 32 do not contain valid data. the actual data shown in figure 22 consists of a 36-bit chain, of which 30 bits are valid led data. the 36-bit data chain is built up as follows: note: the led_data signal is now inverted from the state in mode 0. 5.5.6 power-on, reset, and initialization the led interface is disabled at power-on or reset. the system software controller must enable the led interface. the internal state machines and output pins are held in reset until the full ixf1110 device configuration is completed. 5.5.6.1 enabling the led interface ?led control ($ 0x509)? : this register must be set to globally enable led interface. this is done by setting the led_enable bit to a logic 1. the power-on default for this bit is logic 0. ?port enable ($ 0x500)? : this register enables and disables ports on a per port basis. a port must be enabled for the leds to operate for that port. if the port is not enabled, the leds will be off for that port. the power-on default for this register is 0x3ff, which means all ports are enabled. ?link led enable ($ 0x502)? : this register must be set on a per port basis when link is detected by the system software. this enables the per-port link leds for the ixf1110. link leds do not automatically update. for more details on which leds are affected by this register, refer to section section 5.5.7.1, ?led signaling behavior? on page 86 . figure 22. mode 1 timing table 25. mode 1 clock cycle to data bit relationship led_clk cycle led_data name led_data description 1start bit this bit has no meaning in mode 1 operation and is shifted out of the 32-stage shift register chain before the led_latch signal is asserted. 2:3 pad bits these bits have no meaning in mode 1 operation and are shifted out of the 32-stage shift register chain before the led_latch signal is asserted. 4:33 led data 1-30 these bits are the actual data to be transmitted to the 32-stage shift register chain. the decode for each bit in each mode is defined in table 25 on page 85 . the data is inverted. logic 1 (led on) = low. 34:36 pad bits these bits have no meaning in mode 1 operation and are latched into positions 31 and 32 in the shift register chain. these bits are not considered as valid data and should be ignored. they should always be a logic 0 = high. 1 23 24 25 26 27 28 29 30 135 234 led_clk led_data led_latch 33 32 31 30 29 28 27 26 34 36
intel ? ixf1110 10-port gigabit ethernet media access controller 86 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.5.7 led data decodes table 26 shows the data decode of the data for the ixf1110. 5.5.7.1 led signaling behavior the operation in each mode for the decoded led data in table 26 is detailed in table 27 . table 26. led data decodes led_data# macport # ixf1110 designation 1 0 rx led - amber 2 rx led - green 3 tx led - green 4 1 rx led - amber 5 rx led - green 6 tx led - green 7 2 rx led - amber 8 rx led - green 9 tx led - green 10 3 rx led - amber 11 rx led - green 12 tx led - green 13 4 rx led - amber 14 rx led - green 15 tx led - green 16 5 rx led - amber 17 rx led - green 18 tx led - green 19 6 rx led - amber 20 rx led - green 21 tx led - green 22 7 rx led - amber 23 rx led - green 24 tx led - green 25 8 rx led - amber 26 rx led - green 27 tx led - green 28 9 rx led - amber 29 rx led - green 30 tx led - green
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 87 document number: 250210 revision number: 008 revision date: august 10, 2004 5.6 cpu interface 5.6.1 general description the cpu interface block provides access to registers and statistics in the ixf1110. the interface is asynchronous externally and operates within the 125 mhz clock domain internally. the interface provides access to the following registers: mac control mac rx statistics mac tx statistics global status and configuration rx block tx block spi4-2 block serdes block optical module block figure 23 illustrates the i/o for the cpu interface on the ixf1110. ta ble 2 7. led behavior type status description rxled off synchronization has occurred but no packets are being received and ?link led enable ($ 0x502)? has not been set. amber on rx synchronization has not occurred or no optical signal exists. amber blinking port has remote fault and ?led fault disable ($ 0x50b)? is not set. based on remote fault bit setting received in rx_config word. green on rx synchronization has occurred and the ?link led enable ($ 0x502)? bit is set. green blinking rx synchronization has occurred and port is receiving data. txled off port is not transmitting data or ?link led enable ($ 0x502)? is not set. green blinking port is transmitting data and ?link led enable ($ 0x502)? bit is set note: the led behavior table assumes the port is enabled in the ?port enable ($ 0x500)? and the leds are enabled in the ?led control ($ 0x509)? . if a port is not enabled, all the leds for that port will be off. if the leds are not enabled, all of the leds will be off.
intel ? ixf1110 10-port gigabit ethernet media access controller 88 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.6.2 functional description the cpu interface is designed for a generic 32-bit asynchronous cpu bus. the bus is a 32-bit data bus only and has an 11-bit address bus. the ixf1110 external cpu interface is asynchronous and has no clock. this allows flexibility for cpu selection.the interface to all ixf1110 registers is synchronous to 125 mhz internally. in some applications, synchronous-to-asynchronous glue logic is required between the ixf1110 and the system cpu. this glue logic must be designed so that the ixf1110 read and write access times are not violated. it may be possible to interface without glue logic if the cpu can meet the timing seen in figure 24, ?read timing ? asynchronous interface? on page 90 , figure 25, ?write timing ? asynchronous interface? on page 90 , and table 39, ?cpu timing parameters? on page 109 upx_add[10:0] internal ixf1110 registers and counters are selected using the 11-bit address bus input provided at the cpu interface. this address must be stable for the entire cycle. figure 23. cpu interface inputs/outputs upx_wr_l upx_rd_l upx_cs_l u px_rdy_l upx_data[31:0] upx_addr[10:0] cpu interface 32 11 b3379-0 1 table 28. cpu interface signals name direction standard description upx_add[10:0] input cmos 2.5 v address bus upx_cs_l input cmos 2.5 v chip select signal upx_data[31:0] bi_dir cmos 2.5 v bi-directional data bus upx_wr_l input cmos 2.5 v write strobe upx_rd_l input cmos 2.5 v read strobe upx_rdy_l output cmos 2.5 v cycle complete indicator
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 89 document number: 250210 revision number: 008 revision date: august 10, 2004 upx_cs_l the chip select input when active low selects ixf1110 for the current cycle. no cpu cycle is recognized without this signal being active. at the end of the cycle, the chip select can be driven high to deselect the device or it can be left active if the next access is to the same device (as long as both read and write control signals are inactive between cycles). the cpu usually supports multiple chip selects, and glue logic is required to drive separate chip selects if more than one ixf1110 is being controlled by one cpu. upx_data[31:0] these pins comprise the 32-bit data bus pins containing data to and from the cpu interface. this data is asynchronous on the ixf1110. the write data provided by the cpu must be stable during the entire cpu cycle to prevent erroneous write operations to a register. upx_wr_l this pin indicates there is data on the cpu data bus to be written to the ixf1110. a low-to-high transition latches the data and a high-to-low transition latches the address. this write operation is active low. upx_rd_l this pin indicates there is data on the cpu data bus to be read from the ixf1110. a high-to-low transition latches the address. this read operation is active low. upx_rdy_l this pin indicates the read or write cycle is complete for the ixf1110. this operation is active low. note: external pull-up resistor required for proper operation. 5.6.2.1 read access the ixf1110 read access cycle operation is done in the following order: 1. chip select (upx_cs_l) is asserted at all times for the duration of the operation. the address to be read should be on the ixf1110 address bus (upx_add[10:0]). 2. upx_rd_l should be asserted by the cpu. the ixf1110 latches the address. 3. ixf1110 drives valid data onto the processor bus (upx_data[31:0]). 4. ixf1110 asserts asynchronous-ready (upx_rdy_l). this indicates to the cpu that the read cycle is complete. figure 24 provides the timing of the asynchronous interface for read access.
intel ? ixf1110 10-port gigabit ethernet media access controller 90 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 . 5.6.2.2 write access the ixf1110 write access cycle operation is done in the following order: 1. chip select (upx_cs_l) is asserted at all times for the duration of the operation. the address to be read should be on the ixf1110 address bus (upx_add[10:0]). 2. upx_wr_l should be asserted by the cpu. the ixf1110 latches the address. 3. the cpu drives valid data onto the processor bus (upx_data[31:0]). 4. the cpu de-asserts the asynchronous write signal (upx_wr_l) of the ixf1110. the ixf1110 latches the data. 5. the ixf1110 asserts asynchronous-ready (upx_rdy_l). the glue logic indicates to the cpu that the write cycle is complete. figure 25 provides the timing of the asynchronous interface for write access. figure 24. read timing ? asynchronous interface tcah upx_add[10:0] upx_cs_l upx_rd_l tcrh tcas tcrr tcdrh tcdrs u px_data[31:0] upx_rdy_l tcdrh b3381-0 1 figure 25. write timing ? asynchronous interface t cas t cah t cwl t cdws t cdwd t cyd t cwh upx_add[10:0] upx_wr_l upx_cs_l u px_data[31:0] upx_rdy_l t cdwh b3382-0 1
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 91 document number: 250210 revision number: 008 revision date: august 10, 2004 5.6.2.3 timing parameters timing parameters for the cpu interface are seen in table 39, ?cpu timing parameters? on page 109 . 5.6.3 endian the endian of the cpu interface may be changed to allow connection of various cpus to the ixf1110. the endian selection is determined by setting the endian bit in the ?cpu interface ($ 0x508)? on page 150 ). 5.7 jtag (boundary scan) the ixf1110 includes an ieee 1149.1 boundary scan test port for board level testing. all inputs are accessible. the bsdl file for this device is available by accessing the intel website developer.intel.com. 5.7.1 tap interface (jtag) the ixf1110 includes an ieee 1149.1 compliant test access port (tap) interface used during boundary scan testing. the interface consists of the following five pins: tdi ? serial data input tms ? test mode select tclk ? tap clock trst_l ? active low asynchronous reset for the tap tdo ? serial data output tdi and tms require external pull-up resistors to float the pins high per the ieee 1149.1 specification. pull-ups are recommended on tck and tdo. for normal operation, trst_l can be pulled low, permanently disabling the jtag interface. if the jtag interface is used, the tap controller must be reset as described in section 5.7.2, ?tap state machine? on page 92 and returned to a logic high. note: the jtag pins must be terminated correctly for proper device operation. table 29. recommended jtag termination signal description trst_l 1 pull-down through 10 k ? resistor tdo pull-up through 10 k ? resistor 1. trst_l must be pulled low to ensure proper ixf1110 operation. when trst_l is low, the jtag interface is disabled. if the boundary scan logic is used, trst_l must be pulsed low after power-up to ensure reset of the tap controller. for more information, refer to section 5.7.2, ?tap state machine? on page 92 or the ieee 1149.1 boundary scan specification.
intel ? ixf1110 10-port gigabit ethernet media access controller 92 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.7.2 tap state machine the tap pins drive a tap controller, which implements the 16-state machine specified by the ieee 1149.1 specification. following power up, the tap controller must be reset by one of following two mechanisms: asynchronous reset ? achieved by pulsing or holding trst_l low synchronous reset ? achieved by clocking tck with five clock pulses while tms is held or floats high. this ensures that the boundary scan cells do not block the pin to core connections in theixf1110. 5.7.3 instruction register and supported instructions the instruction register is a 4-bit register that enacts the boundary scan instructions. after the state machine resets, the default instruction is idcode. the decode logic in the tap controller selects the appropriate data register and configures the boundary scan cells for the current instruction. the table below shows the supported boundary scan instructions. 5.7.4 id register the id register is a 32-bit register. the idcode instruction connects this register between tdi and tdo. refer to table 87, ?jtag id revision ($ 0x50c)? on page 152 for register bit descriptions. tdi pull-up through 10 k ? resistor tms pull-up through 10 k ? resistor tck pull-up through 10 k ? resistor table 29. recommended jtag termination signal description 1. trst_l must be pulled low to ensure proper ixf1110 operation. when trst_l is low, the jtag interface is disabled. if the boundary scan logic is used, trst_l must be pulsed low after power-up to ensure reset of the tap controller. for more information, refer to section 5.7.2, ?tap state machine? on page 92 or the ieee 1149.1 boundary scan specification. table 30. supported boundary scan instructions instruction code description data register extest 0000 external test boundary scan sample 0001 sample boundary boundary scan highz 0101 float boundary bypass idcode 0110 id code inspection id clamp 0111 clamp boundary bypass bypass 1111 1-bit bypass bypass
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 93 document number: 250210 revision number: 008 revision date: august 10, 2004 note: the four bit version field is stepping dependent. the seven bit manufacturers id is the intel ? jedec id less the parity bit per the ieee 1149.1 specification. 5.7.5 boundary scan register the boundary scan register is a shift register made up of all the boundary scan cells associated with the device pins. the number, type, and order of the boundary scan cells are specified in the ixf1110 bsdl file. the extest and sample instructions connect this register between tdi and tdo. 5.7.6 bypass register the bypass register is a one bit register that is used so the ixf110 can be bypassed to reduce the length of the jtag chain when trying to access other devices on the chain besides the ixf1110. the bypass, highz, and clamp instructions connect this register between tdi and tdo. 5.8 clocks the ixf1110 has system interface reference clocks, spi4-2 data path input and output clocks, a jtag input clock, a i 2 c output clock, and an led output clock. section 5.8 details the unique clock source requirements. 5.8.1 system interface reference clocks there are two system interface clocks required by the ixf1110: 5.8.1.1 clk125 the system interface clock, which supplies the clock to the majority of the internal circuitry, is the 125 mhz clock. the source of this clock must meet the following specifications: 2.5 v cmos drive +/- 50 ppm maximum duty cycle distortion 40/60 5.8.1.2 clk50 the other system interface clock supplies the clock source to the spi4-2 receive circuitry. the source of this clock must meet the following specifications: 2.5 v cmos drive 1/8 frequency of the spi4-2 data path clock (rdclk_p/n) maximum duty cycle distortion 45/55 maximum peak-to-peak jitter (low and high frequency) of 125 ps range = 40 mhz to 50 mhz
intel ? ixf1110 10-port gigabit ethernet media access controller 94 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5.8.2 spi4-2 receive and transmit data path clocks the spi4-2 data path clocks are compliant with the oif 2000.88.4 specification. the ixf1110 has the following requirements on the transmit data path: 2.5 v lvds drive maximum duty cycle distortion 45/55 maximum peak-to-peak jitter (low and high frequency) of 125 ps stable (frequency and level) when reset is removed or when sourced, whichever happens last tsclk frequency is one-quarter tdclk frequency the ixf1110 meets the following specifications on the receive data path: 2.5 v lvds drive maximum duty cycle distortion 45/55 maximum peak-to-peak jitter (low and high frequency) of 125 ps stable when sourced 5.8.3 jtag clock the ixf1110 supports jtag. the source of this clock must meet the following specifications: 2.5 v cmos drive maximum clock frequency 11 mhz maximum duty cycle distortion 40/60 5.8.4 i 2 c clock the ixf1110 device supports a single output i 2 c clock to support all 10 optical module interfaces. the ixf1110 meets the following specifications for this clock: 2.5 v cmos drive maximum clock frequency of 100 khz 5.8.5 led clock the ixf1110 supports a serial led data stream. this interface implements a 2.5 v cmos output clock with a maximum frequency of 720 hz. the ixf1110 supports a serial led data stream. the ixf1110 meets the following specifications for this clock: 2.5 v cmos drive maximum frequency of 720 hz maximum duty cycle distortion: 50/50
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 95 document number: 250210 revision number: 008 revision date: august 10, 2004 6.0 applications 6.1 power supply sequencing follow the power-up and power-down sequence described in this section to ensure correct ixf1110 operation. the sequence covers all ixf1110 digital and analog supplies. caution: failure to follow the power-up and power-down sequences will damage the ixf1110. 6.1.1 power-up sequence ensure that the 1.8 v supplies (vdd/avdd1p8_1/avdd1p8_2) are applied and stable prior to the application of the 2.5 v supplies (vdd2/avdd2p5_1/avdd2p5_2). caution: if the 2.5 v supplies (vdd2/avdd2p5_1/avdd2p5_2) exceed the 1.8 v (vdd/avdd1p8_1/ avdd1p8_2) supplies by more than 2.0 v during power-up, the esd structures within the analog i/os can be damaged. 6.1.2 power-down sequence the power-down sequence is the reverse of the power-up sequence. remove the 2.5 v supplies prior to removing the 1.8 v supplies. figure 26 and table 31 provide information on power sequencing. note: if the 2.5 v supplies (vdd2/avdd2p5_1/avdd2p5_2) exceed the 1.8 v (vdd/avdd1p8_1/ avdd1p8_2) supplies by more than 2.0 v during power-down, damage can occur to the esd structures within the analog i/os. figure 26. power sequencing time t=0 apply vdd, avdd1p8_1/ 1.8 v supplies stable apply vdd2, avdd2p5_1/ 2.5 v supplies stable apply sys_res_l avdd1p8_2 avdd2p5_2
intel ? ixf1110 10-port gigabit ethernet media access controller 96 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 6.2 analog power filtering figure 32 illustrates an analog power supply filter network and table 32 lists the analog power balls. 6.3 tx fifo and rx fifo operation the intel ? ixf1110 packet buffering is comprised of individual port fifos and system-interface fifos. figure 28 illustrates the interaction of these fifos. table 31. power sequencing power supply power-up order time delta to next supply 1 description vdd, avdd1p8_1 / avdd1p8_2 first 0 1.8 v supplies vdd2, avdd2p5_1 / avdd2p5_2 second 10 s 2.5 v supplies 1. the value of 10 s given is a nominal value only. the exact time difference between the application of the 2.5 v analog supply will be determined by a number of factors dependent on the power management method used. figure 27. analog power supply filter network table 32. analog power balls signal name ball designator comments avdd1p8_1 d1 e24 need to provide a filter (see figure 27 ). r: avdd1p8_1 and avdd2p5_1 = 5.6 ? resistor. avdd2p5_1 y1 avdd1p8_2 p7 v14 p18 v18 v6 v11 need to provide a filter (see figure 27 ). r: avdd1p8_2 and avdd2p5_2 = 1.0 ? resistor. avdd2p5_2 n3 v10 n22 v15 p3 p22 0.1 f vdd 0.1 f analog power ba ll 2.5 or 1.8 v r
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 97 document number: 250210 revision number: 008 revision date: august 10, 2004 6.3.1 tx fifo the ixf1110 tx fifos are implemented with 4.5 kb for each port. this provides enough space for at least one maximum size packet per-port storage and ensures that no under-run conditions occur, assuming that the sending device can supply data at the required data rate. note: the tx fifo high and low watermark must be programmed correctly to ensure that the tx fifo does not overflow. 6.3.1.1 mac transfer threshold the ?tx fifo mac transfer threshold ports 0 to 9 ($ 0x614 - 0x61d)? parameter, which is user programmable, determines when data is transmitted out of the tx fifo to the mac. this parameter is configurable for specific block sizes and the user must ensure that an under-run does not occur. the threshold must be set to a value that exceeds the programmed maxburst1 parameter from the network processor (npu) or spi4-2 asic. this method of operation eliminates the possibility of under-run, except when the controlling npu device fails. the mac transfer threshold operates on a per packet basis. once the number of bytes of a packet received in the tx fifo exceeds the mac transfer th reshold, it will start to be transmitted to the mac. if the mac transfer is greater than the packet size, the packet is sent to the mac once an eop is received. figure 28. packet buffering fifo mdi high water mark data flow mac transfer threshold * low water mark high water mark data flow low water mark rx fifo high txpausefr (external 802.3x pause frame generation strobe) tx fifo tx side mac rx fifo 802.3 flow control rx side mac spi4-2 interface note: the mac transfer threshold determines when the transmit data is transferred from the tx fifo to the tx side of the mac. once the data has been sent from the tx fifo to the mac, it will be transmitted to the phy and cannot be flow controlled from the link partner.
intel ? ixf1110 10-port gigabit ethernet media access controller 98 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 the mac transfer threshold should be set below the table 94, ?tx fifo high watermark ports 0 to 9 ($ 0x600 - 0x609)? on page 162 . if the mac transfer threshold is set above the tx fifo high watermark, the tx fifo high watermark will act as the mac transfer threshold. data is transmitted out of the tx fifo to the mac when the tx fifo high watermark is reached. 6.3.1.2 tx fifo relation to the spi4-2 transmit fifo status (tstat) the amount of data in the tx fifo dictates the fifo status sent to the npu on the tstat bus. the following lists how the fifo status is determined from the tx fifo high and low watermarks. satisfied: the status given for a port when the amount of data in the per port tx fifo is greater than the programmed ?tx fifo high watermark ports 0 to 9 ($ 0x600 - 0x609)? . hungry: the status given for a port when the amount of data in the per port tx fifo is between the programmed ?tx fifo high watermark ports 0 to 9 ($ 0x600 - 0x609)? and the ?tx fifo low watermark ports 0 to 9 ($ 0x60a - 0x613)? . starving: the status given for a port when the amount of data in the per port tx fifo is below the programmed value in ?tx fifo low watermark ports 0 to 9 ($ 0x60a - 0x613)? . note: the user must ensure the tx fifo high and low watermarks are programmed correctly to ensure no underrrun or overflow occur. failure to do this may result in packet loss. 6.3.1.3 tx fifo drain (ixf1110 version) the ixf1110 can allow the spi4-2 npu or asic to dump data to the ixf1110 while the link is down. this allows the npu or asic to empty its fifos, if necessary. the ixf1110 operates in the following manner under normal operating conditions: if the ixf1110 detects that the link is down for a given port, the spi4-2 interface fifo status bus indicates satisfied. this tells the npu or asic that no data can be passed across the spi4-2. the ixf1110 operates in the following the manner when the tx fifo drain is enabled: the spi4-2 fifo status bus indicates starving for the given port. this tells the npu or asic that it can pass data to the ixf1110 for that port, regardless of the link status, and all data sent to that port will be discarded. note: the tx fifo drain is enabled using the section 98, ?tx fifo drain ($0x620)? . 6.3.1.3.1 enabling the tx fifo drain the tx fifo drain is enabled using the ?tx fifo drain ($0x620)? . the following occurs when the tx fifo drain is enabled for a given port: the tx fifo is held in reset the fifo status for that port indicates satisfied all data sent to that port is discarded
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 99 document number: 250210 revision number: 008 revision date: august 10, 2004 6.3.1.3.2 putting the tx fifo in drain mode use the tx fifo drain when the link is down. the following is a step-by-step sequence to put a port(s) into the tx fifo drain mode: 1. the system detects that link is down for a given port using bits 21:20 of the rx config word register ($port_index + 0x16). the spi4-2 tx fifo port status is satisfied when the link is down. 2. set the appropriate bit to 1 for the given port in the tx fifo drain register ($0x620) once link is down. this incurs the following: a. enables the drain mode b. causes the tx fifo for the selected port to enter a reset state c. causes the tx fifo spi4-2 fifo status for that port to change to starving. 3. set the mac soft reset register bit to 1 for the port(s) that has entered the tx fifo drain mode. 4. de-assert the mac soft reset register. redo the mac configurations. if applicable, re- enable auto-negotiation for the selected port(s) by setting bit 5 of the diverse config register back to 1. 5. the connected spi4-2 npu or asic can now dump data to the port(s) that has entered the drain mode. all data sent to the port(s) selected is discarded and not recorded in any register in the ixf1110. 6. monitor the rx config word register to reestablish link with the link partner. exit the tx fifo drain mode when the system software detects link establishment. 6.3.1.3.3 exiting the tx fifo drain mode to exit the tx fifo drain mode. 1. set the tx fifo drain register bits back to 0. this exits the tx fifo drain mode and the tx fifo status bus now indicates the actual tx fifo status. 2. the ixf1110 is ready to resume normal data transmission. 6.3.2 rx fifo the ixf1110 rx fifos are provisioned so that each port has its own 17.0 kb memory space. this is enough memory to ensure against an over-run on any port while transferring normal ethernet frame-size data. the rx fifos are configured by default to automa tically generate pause control frames to initiate the following: halt the link partner when the rx fifo high watermark is reached restart the link partner when the data stored in the rxfifo falls below the low watermark. pause control frame generation is enabled by default in the ?fc enable ($ port_index + 0x12)? . section 8.5.5, ?global rx block register overview? on page 153 documents the registers needed to set the rx fifo watermarks.
intel ? ixf1110 10-port gigabit ethernet media access controller 100 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 note: users should ensure that flow control is enabled to prevent rx fifo overflows. if an rx fifo overflow occurs, data is sent out on the spi4-2 interface regardless of the ?rx fifo errored frame drop enable ($ 0x59f)? settings. the data is marked with an eop abort code to inform the upstream device that this data is corrupted. 6.4 reset and initialization when powering up the ixf1110, the hardware reset signal (sys_res_l) should be held active low for a minimum of 100 ns after all of the power rails have fully stabilized to their nominal values and the input clocks have reached their nominal frequency (tdclk = 400 mhz, clk125 = 125 mhz, and clk50 = 50 mhz). note: in systems where the sys_res_l pin is driven from a single board-wide reset signal, the switch or network processor only comes out of reset at the same time as the ixf1110, or possibly later. this means the tdclk may not be applied to theixf1110 when the sys_res_l pin is released. however, the system designer must ensure that the switch or network processor does not output tdclk until it is stable and has reached its nominal operating frequency. failure to apply a stable tdclk to the ixf1110 can result in the ixf1110 training on a non-stable clock thus causing dip4 errors and data corruption. this will require a re-training once the tdclk is stable. when the tdclk is applied after the reset pin is released, a built-in feature in the ixf1110 reactivates the internal reset once tdclk is applied. the ixf1110 extends this hardware reset internally to ensure synchronization of all internal blocks within the system. the internal reset is extended for a minimum of 4.11 ms after all clocks are stable. the device is correctly initialized at this point and ready for use. clocks start to appear at the relevant device ports and the spi4-2 interface begins to source a training pattern on the receive side while waiting for a training pattern on the transmit side. the spi4-2 interface synchronizes with the connected switch or network processor per the spi4-2 specification. the cpu accesses can begin to configure the device for any existing user preferences desired.by default, all ports on the ixf1110 are enabled after power-up. the device is ready for use at this time if the default settings are to be used. otherwise, access the required registers via the cpu interface and configure the control registers to the required settings. 6.4.1 spi4-2 initialization 6.4.1.1 rx spi4-2 after reset or power-up the rx spi4-2 interface will start to source training patterns on the data bus to the upstream spi4-2 device. the ixf1110 will continue to send the training patterns until a valid calendar is sent on rstat[1:0] from the upstream device to the ixf1110. at this point, synchronization with the upstream device is complete and the ixf1110 will start to send data once data is available and a credit has been granted from the rstat[1:0] bus. when synchronization is completed, bit 13 of the ?spi4-2 rx calendar ($ 0x702)? is ?1?. before completion, bit 13 is ?0?, indicating the ixf1110 is sending out training patterns on the rx spi4-2 data bus.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 101 document number: 250210 revision number: 008 revision date: august 10, 2004 6.4.1.2 tx spi4-2 after reset or power-up, the tx spi4-2 interface outputs a constant framing pattern on tstat until it receives the proper spi4-2 training pattern from the upstream spi4-2 device. for more information on the required training pattern, see ?dynamic phase alignment training sequence (data path de-skew)? on page 65 . note: if tdclk is applied to the ixf1110 after the device has come out of reset, the system designer must ensure the tdclk is stable when applied. failure to due so can result in the ixf1110 training on a non-stable clock, causing dip4 errors and data corruption. once the valid training pattern is received and the ixf1110 outputs a 10-port calendar on tsat, bit 12 of the ?spi4-2 rx calendar ($ 0x702)? on page 173 will be set. this indicates that synchronization on the tx spi4-2 is complete. ports will show a satisfied status on the spi4-2 tstat bus until a valid link is established for that port. to determine if a valid link is established, see ?fiber operation? on page 50 . 6.4.1.3 serdes after reset or power-up the serdes interface will start to output idles on the tx_p/n for forced mode operation. if auto-negotiation mode is required bit 5 of the ?diverse config ($ port_index + 0x18)? on page 137 must be set. a link is established when the rx serdes has received the appropriate code words from the link partner. refer to ?fiber operation? on page 50 for more information. 6.4.1.4 cpu the cpu interface is ready for operation after power-up or reset. through this interface, the user can configure the device for any desired setting from the defaults. (refer to ?cpu interface? on page 87 for more information.) 6.5 serdes power-down capabilities the ixf1110 has the ability to power down the tx and rx serdes individually on each port (see section 5.3, ?serdes interface? on page 70 ). use the following sequence to correctly power up and power down the serdes ports. note: these sequences must be followed to ensure a port correctly operates when brought out of a power- down mode: 6.5.1 placing the serdes port in power-down mode 1. disable the port(s) by de-asserting the appropriate bit(s) in the ?port enable ($ 0x500)? 2. power-down ?serdes tx and rx power-down ports 0-9 ($ 0x787)? 3. the serdes port is now powered down and the tsat status for the port is satisfied
intel ? ixf1110 10-port gigabit ethernet media access controller 102 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 6.5.2 bringing the serdes port out of power-down mode 1. power up tx and rx serdes 2. enable the port(s) by de-asserting the appropriate bit(s) in the ?port enable ($ 0x500)? 3. enable auto-negotiation (if applicable). the device defaults to forced mode if it is not enabled. 4. once a valid link is established, the tstat status bus for that port changes from satisfed to starving. 6.6 ixf1110 unused ports intel recommends the following be used to disable an unused port. the spi4-2 tstat status bus will always reflect status for ten ports regardless of the number of ixf1110 unused ports. any port which is disabled will have a constant status of satisfied. rstat must also be input to reflect the status of all ten ports regardless of how many are disabled. 1. disable ports by setting the appropriate bits in the ?port enable ($ 0x500)? . 2. power down serdes for the unused port by setting the appropriate bits in the ?serdes tx and rx power-down ports 0-9 ($ 0x787)? 3. tx serdes pairs can be left unconnected. 4. rx serdes pairs should be connected to ground 6.7 optical module connections to the ixf1110 6.7.1 sfp-to-ixf1110 connection the ixf1110 serdes and optical module interfaces allow system designers to connect the ixf1110 to various optical transceivers. when using small form factor pluggable (sfp) optical transceivers to connect to the ixf1110, all serdes and optical module status pins are used. use figure 29, ?sfp-to-ixf1110 connection? and table 33, ?sfp-to-ixf1110 connection? to connect an sfp to the ixf1110.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 103 document number: 250210 revision number: 008 revision date: august 10, 2004 figure 29. sfp-to-ixf1110 connection table 33. sfp-to-ixf1110 connection (sheet 1 of 2) sfp pin # sfp pin name ixf1110 pin # 0:9 ixf1110 pin name description 1 veet na na connect to ground. 2txfault m24, v23, y17, r15, w14, w11, w9, ac5, p8, l2 tx_fault_[0:9] use an external 4.7 k ? pull-up resistor to 3.3 v. 3txdisable k22, m22, ac22, u18, u14, aa18, u9, aa9, v7, l4 tx_disable_[0:9] sfp module has internal pull-up. 4 mod_def (2) g22, g23, j24, f22, e23, h24, g20, e22, g24, f24 i 2 c_data_[0:9] use an external 4.7 k ? pull-up resistor to 3.3 v. 5 mod_def (1) l19 i 2 c_clk use an external 4.7 k ? pull-up resistor to 3.3 v. 6 mod_def (0) n24, y21, aa16, m20, ac14, u11, t4, ab2, r7, l1 mod_def_[0:9] use an external 4.7 k ? pull-up resistor to 3.3 v. 7 rate select na na leave floating. 8los l22, v17, ad18, r12, ab15, v12, y9, ac3, t2, p2 rx_los_[0:9] use an external 4.7 k ? pull-up resistor to 3.3 v. 9 veer na na connect to ground. 10 veer na na connect to ground. 11 veer na na connect to ground. t x_f au lt tx_disable tx+ tx- rx+ rx- i 2 c_data i 2 c_clk mod_def rx_los txfault txdis abl e td+ td- rd- rd+ mod_def(0) los mod_def(2) mod_def(1) r ate_sel ect veer 14 vcc r 15 veer 9 veer 11 veer 10 vcct 16 veet 1 veet 17 veet 20 4.7 k ? ixf1110 sfp vdd 3.3 v vdd 3.3 v t x_f au lt_int rx_los_int mod_def_int exter nal cpu 2 4 5 6 3 8 18 19 12 13 7 4.7 k ? vdd 3.3 v 4.7 k ? 4.7 k ? 4.7 k ? 4.7 k ?
intel ? ixf1110 10-port gigabit ethernet media access controller 104 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 12 rd- u22, u20, t24, v24, ab14, ad14, ac16, ad15, v4, y5 rx_n_[0:9] the ixf1110 has a 100 ? differential termination on the chip that requires it to be ac-coupled. ac-coupling is done inside the sfp module and is not required on the host board. 13 rd+ t22, t20, u24, w24, ab13, ad13, ab16, ad16, v5, y6 rx_p_[0:9] 14 veer na na connect to ground. 15 vccr na na connect to filtered 3.3 v. 16 vcct na na connect to filtered 3.3 v. 17 veet na na connect to ground. 18 td+ v20, y19, v22, y23, ab12, ad12, ab9, ad9, t3, t5 tx_p_[0:9] these pins are the differential transmitter inputs. they are ac-coupled differential lines with 100 ? differential termination inside the sfp module. the ac-coupling is done inside the sfp module and is not required on the host board. 19 td- v21, y20, w22, y22, ab11, ad11, ac9, ad10, u3, u5 tx_n_[0:9] 20 veet na na connect to ground. n/a n/a b11 tx_fault_int connect to interrupt service routine. use an external 4.7 k ? pull-up resistor to 3.3 v. n/a n/a b14 rx_los_int connect to interrupt service routine. use an external 4.7 k ? pull-up resistor to 3.3 v. n/a n/a g15 mod_def_int connect to interrupt service routine. use an external 4.7 k ? pull-up resistor to 3.3 v. table 33. sfp-to-ixf1110 connection (sheet 2 of 2) sfp pin # sfp pin name ixf1110 pin # 0:9 ixf1110 pin name description
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 105 document number: 250210 revision number: 008 revision date: august 10, 2004 7.0 electrical specifications table 34 through table 49 on page 121 and figure 30 on page 109 through figure 41 on page 121 represent the target specifications of the following ixf1110 interfaces: ?cpu timing specification? ?jtag timing specification? ?transmit pause control timing specifications? ?optical module interrupt and i2c timing specification? ?system timing specifications? ?led timing specifications? ?serdes timing specification? ?spi4-2 timing specifications? note: these specifications are not guaranteed and are subject to change without notice. minimum and maximum values listed in table 36 through table 49 on page 121 apply over the recommended operating conditions specified in table 34 . table 34. absolute maximum ratings parameter symbol min max units supply voltage vdd -0.3 2.4 volts avdd1p8_1/ avdd1p8_2 -0.3 2.4 volts vdd2 -0.3 3.0 volts avdd2p5_1/ avdd2p5_2 -0.3 3.0 volts operating temperature ambient topa -15 +85 o c case topc ? +130 o c storage temperature tst -65 +125 o c caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
intel ? ixf1110 10-port gigabit ethernet media access controller 106 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 35. operating conditions parameter symbol min typ 1 max units recommended supply voltage vdd, avdd1p8_1, avdd1p8_2 1.71 1.80 1.89 volts vdd2, avdd2p5_1, avdd2p5_2 2.375 2.50 2.625 volts operating current 1000base-sx idd and aidd1p8_1, aidd1p8_2 ? 2.31 2.75 amps idd2 and aidd2p5_1, aidd2p5_2 ? 0.310 0.42 amps recommended operating temperature 2 ambient topa 0 ? 70 o c case with heat sink topc-hs 0 ? 119 o c case without heat sink topc-nhs 0 ? 118 o c recommended storage temperature tost -65 ? 40 o c power consumption 1000base-sx full- duplex all ports enabled and passing data p ? 4.9 6.3 watts 1000base-sx full- duplex six ports enabled and passing data p ? 4.5 5.2 watts 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. 2. refer to the intel? ixf1110 thermal design guidelines (document number 250289).
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 107 document number: 250210 revision number: 008 revision date: august 10, 2004 7.1 dc specifications table 36. 2.5 v lvttl and cmos i/o electrical characteristics parameter symbol min typ 1 max units test conditions input low voltage v il ? ? 0.70 v vcc = min input high voltage 2 v ih 1.7?3.6vvcc = min output low voltage v ol ? ? 0.40 v vcc = min, iol = 3.9 ma output high voltage v oh 2.0 ? ? v vcc = min, ioh = -2.9 ma output leakage current i oz ??10 a vcc = max 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. 2. 3.3 v cmos tolerant. table 37. lvds i/o electrical characteristics parameter symbol min typ 1 max units test conditions input voltage range vi -0.20 ? vddmax+ 0.20 v? differential input voltage |vid| 100 ? ? mv @ 400 mhz input common-mode current icm ? ? ? a lvds input vos = 1.2 v threshold hysteresis th 25 ? ? mv ? differential input impedance r in 85 100 115 ? typical 100 ? output low voltage v ol 0.95 ? ? v ? output high voltage v oh ? ? 1.51 v ? differential output voltage |vod|330?446mv ? delta differential output voltage (complementary states) ? |vod| ? ? 25 mv ? offset (common- mode) voltage vos 1.12 ? 1.30 v ? output leakage current ioz ? ? 10 a? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing.
intel ? ixf1110 10-port gigabit ethernet media access controller 108 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 7.2 undershoot/overshoot specifications the overshoot figures given in this section represent the maximum voltage that can be applied without affecting the reliability of the device (see table 38 ). caution: exceeding these values will damage the device. table 38. undershoot/overshoot limits ball type undershoot overshoot 2.5 v cmos -0.60 v 3.9 v 2.5 v lvttl -0.60 v 3.9 v
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 109 document number: 250210 revision number: 008 revision date: august 10, 2004 7.3 cpu timing specification figure 30. cpu port read timing figure 31. cpu port write timing table 39. cpu timing parameters (sheet 1 of 2) parameter symbol min typ 1 max units test conditions upx_add[12:0], upx_cs_l setup time t cas 10 ? ? ns ? upx_add[12:0], upx_cs_l hold time t cah 10 ? ? ns ? upx_rdy_l assertion to upx_rd_l de-assertion t crr 10 ? ? ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. t cas t cah t crr t cdrs t cdrh t cdrd t crh upx_add[10:0] upx_rd upx_cs upx_data[31:0] upx_rdy t cas t cah t cwl t cdws t cdwd t cyd t cwh upx_add[10:0] upx_wr upx_cs upx_data[31:0] upx_rdy t cdwh
intel ? ixf1110 10-port gigabit ethernet media access controller 110 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 upx_rd_l high width t crh 24 (3x cycle) ??ns ? upx_data[31:0] to upx_rdy_l setup time t cdrs 10 ? ? ns ? upx_data[31:0] to upx_rd_l hold time t cdrh 8?32ns? read upx_data[31:0] driving delay t cdrd 24 ? 355 ns ? upx_wr_l width t cwl 40 ? ? ns ? upx_rdy_l to upx_wr_l hold time t cwh 16 ? ? ns ? upx_data[31:0] to upx_wr_l setup time t cdws 10 ? ? ns ? upx_rdy_l to upx_data[31:0] hold time t cdwh 10 ? ? ns ? upx_data[31:0] latching delay t cdwd 8 ? 40 ns ? upx_rdy_l width in write cycle t cyd 24 ? 40 ns ? read upx_rdy_l de-assertion to upx_wr_l assertion t rtw 32 ? ? ns ? write upx_rdy_l de-assertion to upx_rd_l assertion t wtr 32 ? ? ns ? table 39. cpu timing parameters (sheet 2 of 2) parameter symbol min typ 1 max units test conditions 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 111 document number: 250210 revision number: 008 revision date: august 10, 2004 7.4 jtag timing specification figure 32. jtag timing table 40. jtag timing parameters parameter symbol min typ 1 max units test conditions tclk cycle time t jc 90 ? ? ns ? tclk high time t jh 0.4 x t jc ?0.6 x t jc ns ? tclk low time t jl 0.4 x t jc ?0.6 x t jc ns ? tclk falling edge to tdo valid t jval ??25ns ? tms/tdi setup to tclk t jsu 20 ? ? ns ? tms/tdi hold from tclk t jsh 5??ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. tdo tms, tdi tclk tjval tjl tjh tjc tjsu tjsh
intel ? ixf1110 10-port gigabit ethernet media access controller 112 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 7.5 transmit pause control timing specifications figure 33. transmit pause control interface table 41. transmit pause control interface parameters parameter symbol min typ 1 max units test conditions txpausefr width t pw 16 ? ? ns ? txpauseaddr[3:0] setup to txpausefr t su 16 ? ? ns ? txpauseaddr[3:0] hold from txpausefr t hd 32 ? ? ns ? txpausefr pulse to pulse t btp 48 ? ? ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. txpausefr txpauseaddr[3:0] tbtp tpw tsu thd
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 113 document number: 250210 revision number: 008 revision date: august 10, 2004 7.6 optical module interrupt and i 2 c timing specification figure 34. optical module interrupt timing table 42. optical module interrupt timing parameters parameter symbol min typ 1 max units test conditions change of state on mod_def_9:0 or tx_fault_9:0 or rx_los_9:0 to assertion (active low) on mod_def_int or tx_fault_int or rx_los_int t di 24 ? ? ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. mod_def_9:0 tx_fault_9:0 rx_los_9:0 mod_def_int tx_fault_int rx_los_int tdi
intel ? ixf1110 10-port gigabit ethernet media access controller 114 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 figure 35. i 2 c bus timing figure 36. i 2 c write cycle table 43. i 2 c ac timing characteristics (sheet 1 of 2) parameter symbol min typ 1 max units test conditions clock frequency, scl f scl ??100khz ? clock pulse width low t low 4.7 ? s? clock pulse width high t high 4.0 ? s? noise suppression t i ??100ns ? clock low to data valid out t aa 0.1 ? 4.5 s? time bus must be free before a new transmission starts t buf 4.7 ? ? s? start hold time t hd.sta 4.0 ? ? s? start setup time t su.sta 4.7 ? ? s? data in hold time t hd.dat 0? ? s? data in setup time t su.dat 200 ? ? ns ? inputs rise time t r ??1.0 s? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. i 2 c_clk i 2 c_data out t dh t hd.sta t aa t buf t su.sta t high t r t su.sto t su.dat t hd.dat t low t f i 2 c_data in t low ack 8th bit word n i 2 c_clk i 2 c_data stop condition start condition t wr (1)
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 115 document number: 250210 revision number: 008 revision date: august 10, 2004 inputs fall time t f ??300ns ? stop setup time t su.sto 4.7 ? ? s? data out hold time t dh 100 ? ? ns ? write cycle time t wr ??10ms ? ta ble 4 3. i 2 c ac timing characteristics (sheet 2 of 2) parameter symbol min typ 1 max units test conditions 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing.
intel ? ixf1110 10-port gigabit ethernet media access controller 116 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 7.7 system timing specifications figure 37. hardware reset timing table 44. hardware reset timing parameters parameter symbol min typ 1 max units test conditions reset pulse width t rw 100 ? ? ns ? reset recovery time t rt 4.11 ? ? ms ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. trw trt sys_res _______ cpu access
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 117 document number: 250210 revision number: 008 revision date: august 10, 2004 7.8 led timing specifications figure 38. led timing table 45. led timing parameters parameter symbol min typ 1 max units test conditions 2 led_clk cycle time t cyc 1.36 ? 1.40 ms ? led_clk high time t hi 680 ? 700 s 50% duty cycle led_clk low time t low 680 ? 700 s 50% duty cycle led_clk falling edge to led_data valid t datd 2 ? 5 ns ? led_clk rising edge to led_latch falling edge t hatl 690 ? 700 s ? led_clk falling edge to led_latch rising edge t lath 690 ? 700 s ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. 2. flash rate = 100 ms, led mode 1. led_clk led_data l ed_latch tcyc tlow thi tdatd tha tl tlath
intel ? ixf1110 10-port gigabit ethernet media access controller 118 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 7.9 serdes timing specification table 46 specifies the transmit electrical specifications based on a recommended 1.8 v avdd1p8_1 and avdd1p8_2 termination voltage and the required 50 ? termination and table 46 specifies the receiver electrical specifications based on a recommended 1.8 v avdd1p8_1 and avdd1p8_2 termination voltage. figure 39 illustrates the timing requirements for the ixf1110 transmit and receive serdes signals. note: it is essential that both positive and negative drive levels at the receiver input maintain a minimum voltage of 0.8 v relative to ground to help ensure proper circuit operation. figure 39. serdes timing table 46. transmitter characteristics (sheet 1 of 2) parameter symbol normalized power driver setting min typ 1 max units test conditions transmit differential signal level t v 0.50 180 230 325 mvpp diff avdd1p8_1 and avdd1p8_2 terminated to 1.8 v; r load = 50 ? ; 1.00 350 440 700 1.33 425 580 900 2.00 600 770 1050 transmitter common mode voltage range ? 0.50 1300 1600 1940 mv ? 1.00 1000 1400 1870 1.33 800 1300 1825 2.00 700 1100 1760 transmit eye width t t 1.00 800 ? ? ps ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. note: refer to table 21, ?serdes driver tx power levels? on page 71 for valid serdes power levels. tt rt rv tv
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 119 document number: 250210 revision number: 008 revision date: august 10, 2004 differential signal rise/fall time ? 1.00 60 96 132 ps r load = 50 ? ; 20% to 80% max differential output impedance ? 60 100 150 ? diff dc transmitter short circuit current ? -100 ? 100 ma ? transmitter frequency ? 1.2498 75 1.25 1.25012 5 ghz reference oscillator 125 mhz +/- 100 ppm total transmitter output jitter ? 122 ps p-p total jitter at ber 1e-12 table 47. receiver characteristics parameter symbol min typ 1 max units test conditions receiver differential voltage requirement at center of receive-eye r v 200 ? ? mvp-p diff ? receiver common mode voltage range 900 1275 1650 mv ? receive eye width r t 280 ? ? ps ? receiver termination impedance ?40 ?62.5 ? ? signal detect level ? 125 ? 400 mvp-p diff ? total receiver jitter tolerance ? ? ? 600 ps p-p total jitter at ber 1e-12 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. table 46. transmitter characteristics (sheet 2 of 2) parameter symbol normalized power driver setting min typ 1 max units test conditions 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. note: refer to table 21, ?serdes driver tx power levels? on page 71 for valid serdes power levels.
intel ? ixf1110 10-port gigabit ethernet media access controller 120 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 7.10 spi4-2 timing specifications figure 40. spi4-2 transmit fifo status bus timing table 48. spi4-2 transmit fifo status bus timing parameters parameter symbol min typ 1 max units test conditions tsclk falling edge to tstat[1:0] valid (active edge flipped to falling) t d 1 ? ? 280 ps ? tsclk rising edge to tstat[1:0] valid (default operation) t d 2 ? ? 280 ps ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. tsclk tstat[1:0] tstat[1:0] td2 td1
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 121 document number: 250210 revision number: 008 revision date: august 10, 2004 figure 41. spi4-2 receive fifo status bus timing table 49. spi4-2 receive fifo status bus timing parameters parameter symbol min typ 1 max units test conditions rstat[1:0] setup to rsclk rising edge (default operation) t su 12 ? ? ns ? rstat[1:0] hold from rsclk rising edge (default operation) t h 10.5 ? ? ns ? rstat[1:0] setup to rsclk falling edge (when active edge flipped to falling) t su 22 ? ? ns ? rstat[1:0] hold from rsclk falling edge (when active edge flipped to falling) t h 20.5 ? ? ns ? 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. table 50. spi4-2 lvds rise/fall times parameter symbol min typ max units test conditions rise/fall at source rtsrc ? ? 0.2 ns 400 mhz operation ? measured using conditions set forth in ansi/tia/eia- 644-a-2001 rise/fall at sink rtsnk ? ? 0.4 ns 400 mhz operation ? measured using conditions set forth in ansi/tia/eia- 644-a-2001 rsclk rstat[1:0] rstat[1:0] tsu1 th1 th2 tsu2
intel ? ixf1110 10-port gigabit ethernet media access controller 122 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.0 register definitions 8.1 introduction this section provides information on the location and functionality of the ixf1110 control and status registers. 8.2 document structure this document is structured to give a general overview of the register map and an in-depth description of each bit of a register in later sections. 8.3 graphical representation figure 42 represents an overview of the ixf1110 global control status registers that are used to configure or report on all ports. caution: do not write to any reserved register unless specified. writing to a reserved register address may cause improper device operation.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 123 document number: 250210 revision number: 008 revision date: august 10, 2004 figure 42. memory overview global configuration -rx block configuration -tx block configuraiton port 9 mac control & statistics port 8 mac control & statistics port 7 mac control & statistics port 6 mac control & statistics port 5 mac control & statistics port 0 mac control & statistics port 1 mac control & statistics port2 mac control & statistics port 3 mac control & statistics port 4 mac control & statistics 0x7ff 0x000 0x180 0x100 0x080 0x200 0x280 0x300 0x380 0x400 0x480 0x500
intel ? ixf1110 10-port gigabit ethernet media access controller 124 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.4 per port registers the following section covers all of the registers that are replicated in each of the 10 ports in the ixf1110. these registers perform an identical function in each port. the address vector for the ixf1110 is 11 bits wide. this allows for 7 bits of port-specific access and a 4-bit vector to address each port and all global registers. the address format is shown in figure 43 . 8.5 memory map table 51 through table 59 on page 131 provide theixf1110memory maps. a number of global control and status registers are used to configure or report on all ports, and some registers are replicated on a per-port basis. note: all registers in the ixf1110 are 32 bits. figure 43. register overview port select & global registers per-port registers 10 0 6 table 51. mac control register map (sheet 1 of 2) register bit size mode 1 ref page offset mac control registers (port index + offset) ?station address low ($ port_index + 0x00)? 32 r/w 132 0x00 ?station address high ($ port_index + 0x01)? 32 r/w 132 0x01 reserved 32 ro ? 0x02 ?fdfc type ($ port_index + 0x03)? 32 r/w 132 0x03 reserved 32 r ? 0x04 reserved 32 ro ? 0x05 reserved 32 ro ? 0x06 ?fc tx timer value ($ port_index + 0x07)? 32 r/w 132 0x07 ?fdfc address low ($ port_index + 0x08)? 32 r/w 133 0x08 ?fdfc address high ($ port_index + 0x09)? 32 r/w 133 0x09 reserved 32 r ? 0x0a reserved 32 r ? ox0b ?ipg transmit time ($ port_index + 0x0c)? 32 r/w 133 0x0c reserved 32 r/w -- 0x0d 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 125 document number: 250210 revision number: 008 revision date: august 10, 2004 ?pause threshold ($ port_index + 0x0e)? 32 r/w 134 0x0e ?max frame size ($ port_index + 0x0f)? 32 r/w 134 0x0f reserved 32 ro ? 0x10 reserved 32 ro ? 0x11 ?fc enable ($ port_index + 0x12)? 32 r/w 135 0x12 reserved 32 ro ? 0x13- 0x14 ?discard unknown control frame ($ port_index + 0x15)? 32 r/w 135 0x15 ?rx config word ($ port_index + 0x16)? 32 r/w 135 0x16 ?tx config word ($ port_index + 0x17)? 32 r/w 136 0x17 ?diverse config ($ port_index + 0x18)? 32 r/w 137 0x18 ?rx packet filter control ($ port_index + 0x19)? 32 r/w 138 0x19 ?port multicast address low ($ port_index + 0x1a)? 32 r/w 139 0x1a ?port multicast address high ($ port_index + 0x1b)? 32 r/w 139 0x1b table 52. mac rx statistics register map (sheet 1 of 2) register bit size mode 1 ref page offset mac rx statistics registers (port index + offset) rxoctetstotalok 32 cor 140 0x20 rxoctetsbad 32 cor 140 0x21 rxucpckts 32 cor 140 0x22 rxmcpkts 32 cor 140 0x23 rxbcpkts 32 cor 140 0x24 rxpkts64octets 32 cor 140 0x25 rxpkts65to127octets 32 cor 140 0x26 rxpkts128to255octets 32 cor 140 0x27 rxpkts256to511octets 32 cor 140 0x28 rxpkts512to1023octets 32 cor 140 0x29 rxpkts1024to1518octets 32 cor 140 0x2a rxpkts1519tomaxoctets 32 cor 140 0x2b rxfcserrors 32 cor 140 0x2c rxtagged 32 cor 140 0x2d rxdataerror 32 cor 140 0x2e 1. r = read only; cor = clear on read; w = write; r/w = read/write table 51. mac control register map (sheet 2 of 2) register bit size mode 1 ref page offset mac control registers (port index + offset) 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 126 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 rxalignerrors 32 cor 140 0x2f rxlongerrors 32 cor 140 0x30 rxjabbererrors 32 cor 140 0x31 rxpausemaccontrolcounter 32 cor 140 0x32 rxunknownmaccontrolframecounter 32 cor 140 0x33 rxverylongerrors 32 cor 140 0x34 rxrunterrors 32 cor 140 0x35 rxshorterrors 32 cor 140 0x36 rxcarrierextenderror 32 cor 140 0x37 rxsequenceerrors 32 cor 140 0x38 rxsymbolerrors 32 cor 140 0x39 table 53. mac tx statistics register map (sheet 1 of 2) register bit size mode 1 ref page offset mac tx statistics registers (port index + offset) txoctetstotalok 32 cor 144 0x40 txoctetsbad 32 cor 144 0x41 txucpkts 32 cor 144 0x42 txmcpkts 32 cor 144 0x43 txbcpkts 32 cor 144 0x44 txpkts64octets 32 cor 144 0x45 txpkts65to127octets 32 cor 144 0x46 txpkts128to255octets 32 cor 144 0x47 txpkts256to511octets 32 cor 144 0x48 txpkts512to1023octets 32 cor 144 0x49 txpkts1024to1518octets 32 cor 144 0x4a txpkts1519tomaxoctets 32 cor 144 0x4b txdeferred 32 cor 144 0x4c txtotalcollisions 32 cor 144 0x4d txsinglecollisions 32 cor 144 0x4e txmultiplecollisions 32 cor 144 0x4f txlatecollisions 32 cor 144 0x50 1. r = read only; cor = clear on read; w = write; r/w = read/write table 52. mac rx statistics register map (sheet 2 of 2) register bit size mode 1 ref page offset mac rx statistics registers (port index + offset) 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 127 document number: 250210 revision number: 008 revision date: august 10, 2004 txexcessivecollisionerrors 32 cor 144 0x51 txexcessivedeferralerrors 32 cor 144 0x52 txexcessivelengthdrop 32 cor 144 0x53 txunderrun 32 cor 144 0x54 txtagged 32 cor 144 0x55 txcrcerror 32 cor 144 0x56 txpauseframes 32 cor 144 0x57 txflowcontrolcollisionssend 32 cor 144 0x58 table 54. global status and configuration register map register bit size mode 1 ref page address global status and configuration registers ?port enable ($ 0x500)? 32 r/w 148 0x500 reserved 32 r ? 0x501 ?link led enable ($ 0x502)? 32 r/w 149 0x502 reserved 32 ro ? 0x503 ?core clock soft reset ($ 0x504)? 32 r/w 149 0x504 ?mac soft reset ($ 0x505)? 32 r/w 150 0x505 reserved 32 ro ? 0x506 reserved 32 r ? 0x507 ?cpu interface ($ 0x508)? 32 r/w 150 0x508 ?led control ($ 0x509)? 32 r/w 151 0x509 ?led flash rate ($ 0x50a)? 32 r/w 151 0x50a ?led fault disable ($ 0x50b)? 32 r/w 151 0x50b ?jtag id revision ($ 0x50c)? 32 r/w 152 0x50c 1. r = read only; cor = clear on read; w = write; r/w = read/write table 53. mac tx statistics register map (sheet 2 of 2) register bit size mode 1 ref page offset mac tx statistics registers (port index + offset) 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 128 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 55. rx block register map register bit size mode 1 ref page address rx block registers rx fifo high watermark port 0 32 r/w 153 0x580 rx fifo high watermark port 1 32 r/w 153 0x581 rx fifo high watermark port 2 32 r/w 153 0x582 rx fifo high watermark port 3 32 r/w 153 0x583 rx fifo high watermark port 4 32 r/w 153 0x584 rx fifo high watermark port 5 32 r/w 153 0x585 rx fifo high watermark port 6 32 r/w 153 0x586 rx fifo high watermark port 7 32 r/w 153 0x587 rx fifo high watermark port 8 32 r/w 153 0x588 rx fifo high watermark port 9 32 r/w 153 0x589 rx fifo low watermark port 0 32 r/w 154 0x58a rx fifo low watermark port 1 32 r/w 154 0x58b rx fifo low watermark port 2 32 r/w 154 0x58c rx fifo low watermark port 3 32 r/w 154 0x58d rx fifo low watermark port 4 32 r/w 154 0x58e rx fifo low watermark port 5 32 r/w 154 0x58f rx fifo low watermark port 6 32 r/w 154 0x590 rx fifo low watermark port 7 32 r/w 154 0x591 rx fifo low watermark port 8 32 r/w 154 0x592 rx fifo low watermark port 9 32 r/w 154 0x593 rx fifo number of frames removed on port 0 32 cor 156 0x594 rx fifo number of frames removed on port 1 32 cor 156 0x595 rx fifo number of frames removed on port 2 32 cor 156 0x596 rx fifo number of frames removed on port 3 32 cor 156 0x597 rx fifo number of frames removed on port 4 32 cor 156 0x598 rx fifo number of frames removed on port 5 32 cor 156 0x599 rx fifo number of frames removed on port 6 32 cor 156 0x59a rxfifo number of frames removed on port 7 32 cor 156 0x59b rx fifo number of frames removed on port 8 32 cor 156 0x59c rx fifo number of frames removed on port 9 32 cor 156 0x59d ?rx fifo port reset ($ 0x59e)? 32 r/w 158 0x59e ?rx fifo errored frame drop enable ($ 0x59f)? 32 r/w 159 0x59f ?rx fifo overflow event ($ 0x5a0)? 32 cor 160 0x5a0 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 129 document number: 250210 revision number: 008 revision date: august 10, 2004 table 56. tx block register map (sheet 1 of 2) register bit size mode 1 ref page address tx fifo high watermark port 0 32 r/w 162 0x600 tx fifo high watermark port 1 32 r/w 162 0x601 tx fifo high watermark port 2 32 r/w 162 0x602 tx fifo high watermark port 3 32 r/w 162 0x603 tx fifo high watermark port 4 32 r/w 162 0x604 tx fifo high watermark port 5 32 r/w 162 0x605 tx fifo high watermark port 6 32 r/w 162 0x606 tx fifo high watermark port 7 32 r/w 162 0x607 tx fifo high watermark port 8 32 r/w 162 0x608 tx fifo high watermark port 9 32 r/w 162 0x609 tx fifo low watermark port 0 32 r/w 162 0x60a tx fifo low watermark port 1 32 r/w 163 0x60b tx fifo low watermark port 2 32 r/w 163 0x60c tx fifo low watermark port 3 32 r/w 163 0x60d tx fifo low watermark port 4 32 r/w 163 0x60e tx fifo low watermark port 5 32 r/w 163 0x60f tx fifo low watermark port 6 32 r/w 163 0x610 tx fifo low watermark port 7 32 r/w 163 0x611 tx fifo low watermark port 8 32 r/w 163 0x612 tx fifo low watermark port 9 32 r/w 163 0x613 tx fifo mac transfer threshold port 0 32 r/w 165 0x614 tx fifo mac transfer threshold port 1 32 r/w 165 0x615 tx fifo mac transfer threshold port 2 32 r/w 165 0x616 tx fifo mac transfer threshold port 3 32 r/w 165 0x617 tx fifo mac transfer threshold port 4 32 r/w 165 0x618 tx fifo mac transfer threshold port 5 32 r/w 165 0x619 tx fifo mac transfer threshold port 6 32 r/w 165 0x61a tx fifo mac transfer threshold port 7 32 r/w 165 0x61b tx fifo mac transfer threshold port 8 32 r/w 165 0x61c tx fifo mac transfer threshold port 9 32 r/w 165 0x61d ?tx fifo overflow event ($ 0x61e)? 32 cor 167 0x61e reserved 32 r ? 0x61f ?tx fifo drain ($0x620)? 32 r/w 168 0x620 ?tx fifo info out-of-sequence ($ 0x621)? 32 cor 169 0x621 tx fifo number of frames removed on port 0 32 cor 170 0x622 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 130 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 tx fifo number of frames removed on port 1 32 cor 170 0x623 tx fifo number of frames removed on port 2 32 cor 170 0x624 tx fifo number of frames removed on port 3 32 cor 170 0x625 tx fifo number of frames removed on port 4 32 cor 170 0x626 tx fifo number of frames removed on port 5 32 cor 170 0x627 tx fifo number of frames removed on port 6 32 cor 170 0x628 tx fifo number of frames removed on port 7 32 cor 170 0x629 tx fifo number of frames removed on port 8 32 cor 170 0x62a tx fifo number of frames removed on port 9 32 cor 170 0x62b table 57. spi4-2 block register map register bit size mode 1 ref page address ?spi4-2 rx burst size ($ 0x700)? 32 r/w 172 0x700 ?spi4-2 rx training ($ 0x701)? 32 r/w 172 0x701 ?spi4-2 rx calendar ($ 0x702)? 32 r/w 173 0x702 ?spi4-2 tx synchronization ($ 0x703)? 32 r/w 174 0x703 1. r = read only; cor = clear on read; w = write; r/w = read/write table 58. serdes block register map register bit size mode 1 ref page address reserved 32 ro ? 0x781 reserved 32 ro ? 0x782 reserved 32 ro ? 0x783 ?serdes tx driver power level ports 0-6 ($ 0x784)? 32 ro ? 0x784 ?serdes tx driver power level ports 7-9 ($ 0x785)? 32 ro ? 0x785 reserved 32 ro ? 0x786 ?serdes tx and rx power-down ports 0-9 ($ 0x787)? 32 r/w 175 0x787 reserved 32 ro ? 0x793 reserved 32 ro ? 0x794 reserved 32 ro ? 0x795 reserved 32 ro ? 0x796 reserved 32 ro ? 0x797 reserved 32 ro ? 0x798 1. r = read only; cor = clear on read; w = write; r/w = read/write table 56. tx block register map (sheet 2 of 2) register bit size mode 1 ref page address 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 131 document number: 250210 revision number: 008 revision date: august 10, 2004 table 59. optical module interface block register map register bit size mode 1 ref page address ?optical module status ports 0-9 ($ 0x799)? 32 r 176 0x799 ?optical module control ports 0-9 ($ 0x79a)? 32 r/w 176 0x79a ?i2c control ports 0-9 ($ 0x79b)? 32 r/w 177 0x79b ?i2c data ports 0-9 ($ 0x79c)? 32 r/w 177 0x79c 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 132 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.1 mac control registers table 60 through table 76 on page 139 provide details on the control and status registers associated with each mac port. the register address is ? port_index + 0x** ?, where the port index is set at any value from 0x000 through 0x500. all registers are 32 bits. table 60. station address low ($ port_index + 0x00) bit name description type 1 default 31:0 station address low source mac address bits 31-0. this address is inserted in the source address field when transmitting pause frames, and is also used to compare against unicast pause frames at the receiving side. r/w 0x00000000 1. r = read only; cor = clear on read; w = write; r/w = read/write table 61. station address high ($ port_index + 0x01) bit name description type 1 default 31:16 reserved reserved r 0x0000 15:0 station address high source mac address bits 47-32. this address is inserted in the source address field when transmitting pause frames, and is also used to compare against unicast pause frames at the receiving side. r/w 0x0000 1. r = read only; cor = clear on read; w = write; r/w = read/write table 62. fdfc type ($ port_index + 0x03) bit name description type 1 default 31:16 reserved reserved r 0x0000 15:0 fdfc type contains the value of the type field transmitted in an internally generated flow control (pause) frame. internally generated flow control frames are generated via the external pause interface or when the rx fifo exceeds its high watermark. r/w 0x8808 1. r = read only; cor = clear on read; w = write; r/w = read/write table 63. fc tx timer value ($ port_index + 0x07) bit name description type 1 default 31:16 reserved reserved r 0x0000 15:0 fc tx timer value the pause length sent to the receiving station in 512 bit times r/w 0x005e 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 133 document number: 250210 revision number: 008 revision date: august 10, 2004 table 64. fdfc address low ($ port_index + 0x08) bit name description type 1 default 31:0 fdfc address low contains the value of the lowest 32 bits of the destination address field transmitted in an internally generated flow control (pause) frame. internally generated flow control frames are generated via the external pause interface or when the rx fifo exceeds it high watermark. r/w 0xc2000001 1. r = read only; cor = clear on read; w = write; r/w = read/write table 65. fdfc address high ($ port_index + 0x09) bit name description type 1 default 31:16 reserved reserved r 0x0000 15:0 fdfc address high contains the value of the highest 16 bits of the destination address filed transmitted in an internally generated flow control (pause) frame. internally generated flow control frames are generated via the external pause interface or when the rx fifo exceeds it high watermark. r/w 0x0180 1. r = read only; cor = clear on read; w = write; r/w = read/write table 66. ipg transmit time ($ port_index + 0x0c) bit name description type 1 default 31:10 reserved reserved r 0x0000 9:0 ipg transmit time ipg time for back-to-back transmissions (specified in multiples of 8 bit times). the value specified in this register is calculated as follows: (register value + 4) *8 = ipg length in terms of bit times. therefore, the default value of 8 gives: (8+4) *8 = 96 bit times. 96 bit times is the minimum ipg. if a value of 8 or less is written to this register, the ipg remains 96 bit times. r/w 0x0008 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 134 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 67. pause threshold ($ port_index + 0x0e) bit name description type 1 default 31:16 reserved reserved r 0x0000 15:0 pause threshold when a pause frame is sent, an internal timer checks when a new pause frame must be scheduled for transmission to keep the link partner in pause mode. the pause threshold value is the minimum time to send before the earlier pause frame is aged out (specified in multiples of 512 bit times). note: the value in this register is subtracted from the value in the ?fc tx timer value ($ port_index + 0x07)? to set the internal pause threshold. this value determines how often a pause frame is sent out to keep the link partner in pause mode. r/w 0x002f 1. r = read only; cor = clear on read; w = write; r/w = read/write table 68. max frame size ($ port_index + 0x0f) bit name description type 1 default 31:14 reserved reserved r 0x0000 13:0 max frame size the maximum frame size the mac can receive or transmit without activating any error counters, and without truncation. the maximum frame size is internally adjusted by +4 if vlan is tagged. r/w 0x05ee 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 135 document number: 250210 revision number: 008 revision date: august 10, 2004 table 69. fc enable ($ port_index + 0x12) bit name description type 1 default register description: indicates which flow control mode is used for the rx and tx mac. 0x00000007 31:2 reserved reserved r 0x00000000 1tx fdfc 0 = disable tx full-duplex flow control [the mac will not generate internally any flow control frames based on the rx fifo watermarks or the transmit pause control interface 1 = enable tx full-duplex flow control [enables the mac to send flow control frames to the link partner based on the rx fifo programmable watermarks or the transmit pause control interface] r/w 1 0rx fdfc 0 = disable rx full-duplex flow control [the mac will not respond to flow control frames sent to it by the link partner] 1 = enable rx full-duplex flow control [mac will respond to flow control frames sent by the link partner and will stop packet transmission for the time specified in the flow control frame] r/w 1 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 70. discard unknown control frame ($ port_index + 0x15) bit name description type 1 default 31:1 reserved reserved r 0x00000000 0 discard unknown control frame 0 = keep unknown control frames 1 = discard unknown control frames. r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write table 71. rx config word ($ port_index + 0x16) (sheet 1 of 2) bit name description type 1 default register description: this register is used in the ixf1110 only for auto-negotiation. register bits 15:0 are the ?config_word? received from the link partner, as described in ieee 802.3, sub clause 37.2.1. 0x00000000 31:22 reserved ro 0 21 an_complete auto-negotiation complete. this bit remains cleared from the time auto-negotiation is reset until auto- negotiation reaches the ?link_ok? state. it remains set until auto-negotiation is disabled or restarted. (this bit is only valid if auto-negotiation is enabled.) r0 20 rx sync 0 = loss of synchronization 1 = bit synchronization (bit remains low until register is read) cor 0 19 rx config 0 = receiving idle/data stream 1 = receiving /c/ ordered sets r 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 136 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 18 config changed 0 = rxconfigword has changed since last read 1 = rxconfigword has not changed since last read (this bit remains high until register is read) cor 0 17 invalid word 0 = have not received an invalid symbol 1 = have received an invalid symbol (this bit remains high until register is read) cor 0 16 carrier sense 0 = device is not receiving idle characters (carrier sense is true). 1 = device is receiving idle characters (carrier sense is false). r0 15 next page next page request r 0 14 reserved reserved r 0 13:12 remotefault[1:0] remote fault definitions: 00 = no error, link okay 01 = offline 10 = link failure 11 = auto-negotiation_error r00 11:9 reserved reserved r 000 8 asym pause asym pause (ability to send pause frames) r 0 7 sym pause sym pause (ability to send and receive pause frames) r 0 6 half duplex half-duplex r 0 5 full duplex full-duplex r 0 4:0 reserved reserved r 00000 table 72. tx config word ($ port_index + 0x17) (sheet 1 of 2) bit name description type 1 default register description: this register is used in the ixf1110 for auto-negotiation only. the contents of this register are sent as the config_word. 0x000001a0 31:16 reserved reserved r 0x0000 15 nextpage next page request r/w 0 14 reserved 3 write as 0, ignore on read r/w 0 13:12 2 remote fault [1:0] remote fault definitions: 00 =no error, link okay 01 = offline 10 =link failure 11 = auto-negotiation_error r/w 00 11:9 reserved 3 write as 0, ignore on read r/w 000 8 asym pause ability to send pause frames r/w 1 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. there is no way to automatically update the state of the remote fault bits for transmission. the state of these bits must be set by the system controller through the up interface prior to enabling auto-negotiation. 3. reserved bits must be written to ?0? to prevent illegal advertisement. table 71. rx config word ($ port_index + 0x16) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 137 document number: 250210 revision number: 008 revision date: august 10, 2004 7 sym pause ability to send and receive pause frames r/w 1 6 half duplex half-duplex r/w 0 5 full duplex full-duplex r/w 1 4:0 reserved 3 write as 0, ignore on read r/w 00000 table 73. diverse config ($ port_index + 0x18) bit name description type 1 default register description: this register contains various configuration bits for general use. 0x0000110d 31:19 reserved reserved r 0x0000 18:13 reserved write as 0, ignore on read r/w 000000 12 reserved 2 write as 1, ignore on read r/w 1 11:9 r eserved 2 write as 0, ignore on read r/w 000 8 reserved 2 write as 1, ignore on read r/w 1 7 pad_enable enable padding of undersized packets r/w 0 6 crc_add enable automatic crc appending r/w 0 5 an_enable auto-negotiation enable: 1 = setting this bit to 1 puts the port in an auto-negotiation mode and starts auto- negotiation. 0 = setting this bit to 0 disables auto- negotiation and puts the ixf1110 in forced mode. note: since default = 0, this bit must be changed to a 1 via the cpu to enable auto- negotiation. auto-negotiation can be restarted by de-asserting this bit, then re- asserting. r/w 0 4 2 reserved write as 0, ignore on read r/w 0 3:2 2 reserved write as 1, ignore on read r/w 11 1 2 reserved write as 0, ignore on read r/w 0 0 2 reserved write as 1, ignore on read r/w 1 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. reserved bits must be written to the default value for proper operation table 72. tx config word ($ port_index + 0x17) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. there is no way to automatically update the state of the remote fault bits for transmission. the state of these bits must be set by the system controller through the up interface prior to enabling auto-negotiation. 3. reserved bits must be written to ?0? to prevent illegal advertisement.
intel ? ixf1110 10-port gigabit ethernet media access controller 138 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 74. rx packet filter control ($ port_index + 0x19) (sheet 1 of 2) bit name description type 1 default register description: this register allows for specific packet types to be marked for filtering, and is used in conjunction with the rx fifo errored frames drop enable register 0x00000000 31:6 reserved reserved r 0x000000 5 crc error pass 2 this bit enables a global filter on frames with a crc error. when crcerrorpass = 0, all frames with a crc error are marked as bad. note: when used in conjunction with the rx fifo erroredframedropenable[9:0] register (see table 92 on page 159 ). this allows the frame to be dropped in the rx fifo. otherwise, the frame is sent across the spi4-2 interface but marked as an eop abort frame. when the crc error pass filter bit = 0, it takes precedence over the other filter bits. any packet regardless if it is a pause, unicast, multicast or broadcast packet with a crc error will be marked as bad frames when crc error pass = 0 when crcerrorpass = 1, frames with a crc error are not marked as bad and are passed to the spi4-2 interface for transfer as good frames, regardless of the state of the framedropen[9:0] bits. r/w 0 4 pause frame pass this bit enables a global filter on pause frames. when pauseframepass = 0, all pause frames are marked as bad. note: when used in conjunction with the rx fifo erroredframedropenable[9:0] register (see table 92 on page 159 ). this allows the frame to be dropped in the rx fifo. otherwise, the frame is sent across the spi4-2 interface but marked as an eop abort frame. note: when pauseframepass = 1, all pause frames are not marked as bad and are passed to the spi4-2 interface for transfer as good frames, regardless of the state of the framedropen[9:0] bits. r/w 0 3 vlan drop en 2 this bit enables a global filter on vlan frames. when vlandropen = 0, all vlan frames are passed to the spi4-2 interface. when vlandropen = 1, all vlan frames are dropped. 3 r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. jumbo frames (1519 - 9600 bytes), matching the filter conditions, which would cause the frame to be dropped by the rx fifo, will not be dropped. instead, jumbo frames that are marked to be dropped by the rx fifo, based on the filter setting in this register, will still be sent across the spi4-2 interface, but will be marked as an eop abort frame. thus, jumbo frames matching the filter conditions will not be counted in the rx fifo number of frames removed register because they are not removed by the rx fifo. only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be dropped by the rx fifo and counted in the rx fifo number of frames removed. 3. frames are dropped only when the appropriate bits are set in the rx fifo errored frame drop enable register ( table 92 on page 159 ). when the appropriate bits are not set, the frames are sent across the spi4-2 interface and marked as eop abort frames.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 139 document number: 250210 revision number: 008 revision date: august 10, 2004 2 b/cast drop en 2 this bit enables a global filter on broadcast frames. when b/castdropen = 0, all broadcast frames are passed to the spi4-2 interface. when b/castdropen = 1, all broadcast frames are dropped. 3 r/w 0 1 m/cast match en 2 this bit enables a filter on multicast frames. if this bit = 0, all multicast frames are good and are passed to the spi4-2 interface. if this bit = 1, only multicast frames with a destination address that matches the portmulticastaddress is forwarded. all other multicast frames are dropped. 3 r/w 0 0 u/cast match en 2 this bit enables a filter on unicast frames. if this bit = 0, all unicast frames are good and are passed to the spi4-2 interface. if this bit = 1, only unicast frames with a destination address that matches the station address is forwarded. all other unicast frames are dropped. 3 note: the vlan filter overrides the unicast filter. thus, a vlan frame cannot be filtered based on the unicast address. r/w 0 table 75. port multicast address low ($ port_index + 0x1a) bit name description type 1 default 31:0 port multicast address low this address is used to compare against multicast frames at the receiving side if multicast filtering is enabled. this register contains bits 31:0 of the address. r/w 0x00000000 1. r = read only; cor = clear on read; w = write; r/w = read/write table 76. port multicast address high ($ port_index + 0x1b) bit name description type 1 default 31:16 reserved reserved r 0x0000 15:0 port multicast address high this address is used to compare against multicast frames at the receiving side if multicast filtering is enabled. this register contains bits 47:32 of the address. r/w 0x0000 1. r = read only; cor = clear on read; w = write; r/w = read/write table 74. rx packet filter control ($ port_index + 0x19) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. jumbo frames (1519 - 9600 bytes), matching the filter conditions, which would cause the frame to be dropped by the rx fifo, will not be dropped. instead, jumbo frames that are marked to be dropped by the rx fifo, based on the filter setting in this register, will still be sent across the spi4-2 interface, but will be marked as an eop abort frame. thus, jumbo frames matching the filter conditions will not be counted in the rx fifo number of frames removed register because they are not removed by the rx fifo. only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be dropped by the rx fifo and counted in the rx fifo number of frames removed. 3. frames are dropped only when the appropriate bits are set in the rx fifo errored frame drop enable register ( table 92 on page 159 ). when the appropriate bits are not set, the frames are sent across the spi4-2 interface and marked as eop abort frames.
intel ? ixf1110 10-port gigabit ethernet media access controller 140 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.2 mac rx statistics register overview the mac rx statistics registers contain the mac receiver statistic counters and are cleared when read. the software polls these registers and accumulates values to ensure that the counters do not wrap. the 32-bit counters wrap after approximately 30 seconds. table 77 covers the mac rx statistics registers for all 10 mac ports. the address is identical to the port number. table 77. mac rx statistics ($ port_index + 0x20 - port_index + 0x39) (sheet 1 of 4) name description address type 1 default rxoctetstotalok counts the bytes received in all legal frames, including all bytes from the destination mac address to and including the crc. the initial preamble and sfd bytes are not counted. port_index + 0x20 cor 0x00000000 rxoctetsbad 2 counts the bytes received in all bad frames of a size greater than or equal to 64 bytes. a bad frame is defined as a properly framed packet containing a crc, alignment error, or code violation. the 64-byte value is measured from the destination address, up to and including crc. the initial preamble and sfd are not included in this value. note: this register does not increment the bad octet count on undersized receive packets. port_index + 0x21 cor 0x00000000 rxucpkts the total number of unicast packets received (excluding bad packets) note: this count includes non-pause control and vlan packets, which are also counted in other counters. these packet types are counted twice. take care when summing register counts for reporting mib information. port_index + 0x22 cor 0x00000000 rxmcpkts the total number of multicast packets received (excluding bad packets) note: this count includes pause control packets, which are also counted in the pausemaccontrol- receivedcounter. these packet types are counted twice. take care when summing register counts for reporting mib information. port_index + 0x23 cor 0x00000000 rxbcpkts the total number of broadcast packets received (excluding bad packets) port_index + 0x24 cor 0x00000000 rxpkts64octets the total number of packets received (including bad packets) that were 64 octets in length. incremented for tagged packets with a length of 64 bytes, including tag field port_index + 0x25 cor 0x00000000 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. when sending in large frames, the counters can only deal with certain limits. the behavior of the longerrors and verylongerrors counters is as follows: verylongerrors counts frames that are 2*maxframesize, dependent on where the maxframesize variable is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never incremented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. maxframesize is determined by the settings in the ?max frame size ($ port_index + 0x0f)? on page 134 .
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 141 document number: 250210 revision number: 008 revision date: august 10, 2004 rxpkts65to127 octets the total number of packets received (including bad packets) that were [65-127] octets in length. incremented for tagged packets with a length of 65 - 127 bytes, including tag field port_index + 0x26 cor 0x00000000 rxpkts128to255 octets the total number of packets received (including bad packets) that were [128-255] octets in length. incremented for tagged packets with a length of 128-255 bytes, including tag field port_index + 0x27 cor 0x00000000 rxpkts256to511 octets the total number of packets received (including bad packets) that were [256-511] octets in length. incremented for tagged packets with a length of 256 - 511 bytes, including tag field port_index + 0x28 cor 0x00000000 rxpkts512to1023 octets the total number of packets received (including bad packets) that were [512-1023] octets in length. incremented for tagged packets with a length of 512 - 1023 bytes, including tag field port_index + 0x29 cor 0x00000000 rxpkts1024to1518 octets the total number of packets received (including bad packets) that were [1024-1518] octets in length. incremented for tagged packet with a length between 1024-1522, including the tag port_index + 0x2a cor 0x00000000 rxpkts1519tomax octets the total number of packets received (including bad packets) that were >1518 octets in length. incremented for tagged packet with a length between 1523-max frame size, including the tag port_index + 0x2b cor 0x00000000 rxfcserrors number of frames received with legal size, but with wrong crc field (also called fcs field) note: legal size is 64 bytes through the value stored in the ?max frame size ($ port_index + 0x0f)? on page 134 . port_index + 0x2c cor 0x00000000 rxtagged number of frames with vlan tag (type field = 0x8100) port_index + 0x2d cor 0x00000000 rxdataerror number of frames received with legal length, containing a code violation (signaled with rx_err on rgmii) note: the ixf1110 does not support an rgmii interface; thus, this counter is not applicable to the ixf1110. port_index + 0x2e cor 0x00000000 rxalignerrors note: number of frames with a legal frame size, but containing less than 8 additional bits. this occurs when a frame is not byte-aligned. the crc of the frame is wrong when the additional bits are stripped. if the crc is ok, the frame is not counted, but treated as an ok frame.the ixf1110 does not support an rgmii interface; thus, this counter is not applicable to the ixf1110 port_index + 0x2f cor 0x00000000 table 77. mac rx statistics ($ port_index + 0x20 - port_index + 0x39) (sheet 2 of 4) name description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. when sending in large frames, the counters can only deal with certain limits. the behavior of the longerrors and verylongerrors counters is as follows: verylongerrors counts frames that are 2*maxframesize, dependent on where the maxframesize variable is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never incremented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. maxframesize is determined by the settings in the ?max frame size ($ port_index + 0x0f)? on page 134 .
intel ? ixf1110 10-port gigabit ethernet media access controller 142 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 rxlongerrors 2 frames bigger than the maximum allowed, with both ok crc and the integral number of octets default maximum allowed is 1518 bytes untagged and 1522 bytes tagged, but the value can be changed by a register frames bigger than the larger of 2*maxframesize and 50000 bits are not counted here, but counted in the verylongerror counter. port_index + 0x30 cor 0x00000000 rxjabbererrors frames bigger than the maximum allowed, with either a bad crc or a non-integral number of octets. the default maximum allowed is 1518 bytes untagged and 1522 bytes tagged, but the value can be changed by a register. frames bigger than the larger of 2*maxframesize and 50000 bits are not counted here, but counted in the verylongerror counter. port_index + 0x31 cor 0x00000000 rxpausemac controlcounter number of pause mac control frames received this statistic register increments on any valid 64byte pause frame with valid crc and will also increment on 64byte pause frames with an invalid crc if bit 5 of the ?rx packet filter control ($ port_index + 0x19)? is set to 1. port_index + 0x32 cor 0x00000000 rxunknownmac controlframe counter number of mac control frames received with an op code different from 0001 (pause) port_index + 0x33 cor 0x00000000 rxverylongerrors 2 frames bigger than the larger of 2*maxframesize and 50000 bits port_index + 0x34 cor 0x00000000 rxrunterrors the total number of packets received that are less than 64 octets in length, but longer than or equal to 96 bit times. note: rxrunterrors is not supported in the ixf1110. any runt or short packets received are not counted in this register. note: the ?shortruntsthreshold? register controls the byte count used to determine the difference between runts and shorts, and therefore controls which counter is incremented for a given frame size. this counter is only updated after receipt of two good frames. port_index + 0x35 cor 0x00000000 table 77. mac rx statistics ($ port_index + 0x20 - port_index + 0x39) (sheet 3 of 4) name description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. when sending in large frames, the counters can only deal with certain limits. the behavior of the longerrors and verylongerrors counters is as follows: verylongerrors counts frames that are 2*maxframesize, dependent on where the maxframesize variable is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never incremented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. maxframesize is determined by the settings in the ?max frame size ($ port_index + 0x0f)? on page 134 .
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 143 document number: 250210 revision number: 008 revision date: august 10, 2004 rxshorterrors the total number of packets received that are less than 96 bit times, which corresponds to a 4- byte frame with a well formed preamble and sfd. this counter indicates fragment sizes illegal in all modes, and is only fully updated after reception of a good frame following a fragment. note: rxshorterrors is not supported in the ixf1110. any runt or short packets received are not counted in this register. port_index + 0x36 cor 0x00000000 rxcarrierextend error gigabit half-duplex event only note: n/a - half-duplex only port_index + 0x37 cor 0x00000000 rxsequenceerrors records the number of sequencing errors that occur. port_index + 0x38 cor 0x00000000 rxsymbolerrors records the number of symbol errors encountered. port_index + 0x39 cor 0x00000000 table 77. mac rx statistics ($ port_index + 0x20 - port_index + 0x39) (sheet 4 of 4) name description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. when sending in large frames, the counters can only deal with certain limits. the behavior of the longerrors and verylongerrors counters is as follows: verylongerrors counts frames that are 2*maxframesize, dependent on where the maxframesize variable is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never incremented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. maxframesize is determined by the settings in the ?max frame size ($ port_index + 0x0f)? on page 134 .
intel ? ixf1110 10-port gigabit ethernet media access controller 144 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.3 mac tx statistics register overview the mac tx statistics registers contain all the mac transmit statistic counters and are cleared when read. the software must poll these registers to accumulate values and ensure that the counters do not wrap. the 32-bit counters wrap after approximately 30 seconds. table 78 covers the mac tx statistics registers for all 10 mac ports. the address is identical to the port number. table 78. mac tx statistics ($ port_index + 0x40 - port_index + 0x58) (sheet 1 of 4) name description address type 1 default txoctetstotalok counts the bytes transmitted in all legal frames. the count includes all bytes from the destination mac address to and including the crc. the initial preamble and sfd bytes are not counted. port_index + 0x40 cor 0x00000000 txoctetsbad counts the bytes transmitted in all bad frames. the count includes all bytes from the destination mac address to and including the crc. the initial preamble and sfd bytes are not counted. tx underrun counted: the count is expected to match the number of bytes actually transmitted before the frame is discarded. tx crc error counted: all bytes not sent with success are counted by this counter port_index + 0x41 cor 0x00000000 txucpkts the total number of unicast packets transmitted (excluding bad packets) port_index + 0x42 cor 0x00000000 txmcpkts the total number of multicast packets transmitted (excluding bad packets) note: this count includes pause control packets which are also counted in the txpauseframes counter. thus, these types of packets are counted twice. take care when summing register counts for reporting mib information. port_index + 0x43 cor 0x00000000 txbcpkts the total number of broadcast packets transmitted (excluding bad packets) port_index + 0x44 cor 0x00000000 txpkts64octets the total number of packets transmitted (including bad packets) that were 64 octets in length. incremented for tagged packets with a length of 64 bytes, including tag field port_index + 0x45 cor 0x00000000 txpkts65to127octets the total number of packets transmitted (including bad packets) that were [65-127] octets in length. incremented for tagged packets with a length of 65 - 127 bytes, including tag field port_index + 0x46 cor 0x00000000 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 145 document number: 250210 revision number: 008 revision date: august 10, 2004 txpkts128to255octets the total number of packets transmitted (including bad packets) that were [128-255] octets in length. incremented for tagged packets with a length of 128 - 255 bytes, including tag field port_index + 0x47 cor 0x00000000 txpkts256to511octets the total number of packets transmitted (including bad packets) that were [256-511] octets in length. incremented for tagged packets with a length of 256 - 511 bytes, including tag field port_index + 0x48 cor 0x00000000 txpkts512to1023octets the total number of packets transmitted (including bad packets) that were [512 - 1023] octets in length. incremented for tagged packets with a length of 512 - 1023 bytes, including tag field port_index + 0x49 cor 0x00000000 txpkts1024to1518octets the total number of packets transmitted (including bad packets) that were [1024-1518] octets in length. incremented for tagged packet with a length between 1024-1522, including the tag port_index + 0x4a cor 0x00000000 txpkts1519tomaxoctets the total number of packets transmitted (including bad packets) that were >1518 octets in length. incremented for tagged packet with a length between 1523-max frame size, including the tag port_index + 0x4b cor 0x00000000 txdeferred number of times the initial transmission attempt of a frame is postponed due to another frame already being transmitted on the ethernet network. note : n/a - half-duplex only port_index + 0x4c cor 0x00000000 txtotalcollisions sum of all collision events note : n/a - half-duplex only port_index + 0x4d cor 0x00000000 txsinglecollisions a count of successfully transmitted frames on a particular interface where the transmission is inhibited by exactly one collision. a frame that is counted by an instance of this object is also counted by the corresponding instance of either the unicastpkts, multicastpkts, or broadcastpkts, and is not counted by the corresponding instance of the multiplecollisionframes object. note : n/a - half-duplex only port_index + 0x4e cor 0x00000000 table 78. mac tx statistics ($ port_index + 0x40 - port_index + 0x58) (sheet 2 of 4) name description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 146 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 txmultiplecollisions a count of successfully transmitted frames on a particular interface for which transmission is inhibited by more than one collision. a frame that is counted by an instance of this object is also counted by the corresponding instance of either the unicastpkts, multicastpkts, or broadcastpkts, and is not counted by the corresponding instance of the singlecollisionframes object. note : n/a - half-duplex only port_index + 0x4f cor 0x00000000 txlatecollisions the number of times a collision is detected on a particular interface later than 512 bit-times into the transmission of a packet. such frame are terminated and discarded. note : n/a - half-duplex only port_index + 0x50 cor 0x00000000 txexcessivecollisionerrors a count of frames, which collides 16 times and is then discarded by the mac. not effecting xmultiplecollisions note: n/a - half-duplex only port_index + 0x51 cor 0x00000000 txexcessivedeferralerrors number of times frame transmission is postponed more than 2*maxframesize due to another frame already being transmitted on the ethernet network. this causes the mac to discard the frame. note : n/a - half-duplex only port_index + 0x52 cor 0x00000000 txexcessivelengthdrop frame transmissions aborted by the mac because the frame is longer than maximum frame size. these frames are truncated by the mac when the maximum frame size violation is detected by the mac. port_index + 0x53 cor 0x00000000 txunderrun internal tx error which causes the mac to end the transmission before the end of the frame because the mac did not get the needed data in time for transmission. the frames are lost and a fragment or a crc error is transmitted. port_index + 0x54 cor 0x00000000 txtagged number of ok frames with vlan tag. (type field = 0x8100). port_index + 0x55 cor 0x00000000 table 78. mac tx statistics ($ port_index + 0x40 - port_index + 0x58) (sheet 3 of 4) name description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 147 document number: 250210 revision number: 008 revision date: august 10, 2004 txcrcerror number of frames transmitted with a legal size, but with the wrong crc field (also called fcs field) port_index + 0x56 cor 0x00000000 txpauseframes number of pause mac frames transmitted port_index + 0x57 cor 0x00000000 txflowcontrolcollisions send collisions generated on purpose on incoming frames, to avoid reception of traffic, while the port is in half-duplex and has flow control enabled, and do not have sufficient memory to receive more frames. note: due to the internal counting technique, a last frame might have to be transmitted after last flow control collision send to get the correct statistic. note : n/a - half-duplex only port_index + 0x58 cor 0x00000000 table 78. mac tx statistics ($ port_index + 0x40 - port_index + 0x58) (sheet 4 of 4) name description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 148 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.4 global status and configuration register overview table 79 through table 86 on page 151 provide an overview of the global control and status registers. table 79. port enable ($ 0x500) bit name description type 1 default register description: a control register for each port in the ixf1110. port id = bit position in the register. to make a port active, the bit must be set high (for example, port 4 active implies register value = 0001.0000). setting the bit to 0 disables the port. the default state for this register is for all 10 ports to be active. 0x000003ff 31:10 reserved reserved r 0x00000 9 port 9 enable port 9 0 = disable 1 = enable r/w 1 8 port 8 enable port 8 0 = disable 1 = enable r/w 1 7 port 7 enable port 7 0 = disable 1 = enable r/w 1 6 port 6 enable port 6 0 = disable 1 = enable r/w 1 5 port 5 enable port 5 0 = disable 1 = enable r/w 1 4 port 4 enable port 4 0 = disable 1 = enable r/w 1 3 port 3 enable port 3 0 = disable 1 = enable r/w 1 2 port 2 enable port 2 0 = disable 1 = enable r/w 1 1 port 1 enable port 1 0 = disable 1 = enable r/w 1 0 port 0 enable port 0 0 = disable 1 = enable r/w 1 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. if a port is disabled mid-packet on the receive side in serdes mode, the rx stats will not update for that packet due to power-down of serdes when the port is disabled.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 149 document number: 250210 revision number: 008 revision date: august 10, 2004 table 80. link led enable ($ 0x502) bit name description type 1 default register description: per-port bit should be set upon detection of link by system cpu to enable proper operation of the link leds. 0x00000000 31:10 reserved reserved r 0x00000 9 link led enable port 9 port 9 link 0 = no link 1 = link r/w 0 8 link led enable port 8 port 8 link 0 = no link 1 = link r/w 0 7 link led enable port 7 port 7 link 0 = no link 1 = link r/w 0 6 link led enable port 6 port 6 link 0 = no link 1 = link r/w 0 5 link led enable port 5 port 5 link 0 = no link 1 = link r/w 0 4 link led enable port 4 port 4 link 0 = no link 1 = link r/w 0 3 link led enable port 3 port 3 link 0 = no link 1 = link r/w 0 2 link led enable port 2 port 2 link 0 = no link 1 = link r/w 0 1 link led enable port 1 port 1 link 0 = no link 1 = link r/w 0 0 link led enable port 0 port 0 link 0 = no link 1 = link r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write table 81. core clock soft reset ($ 0x504) bit name description type 1 default register description : a soft reset register for the core clock system (for example, the sys125 clock). 0x00000000 31:1 reserved reserved r 0x00000000 0 core soft reset 0 = coresoftreset reset is inactive 1 = coresoftreset reset is active r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 150 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 82. mac soft reset ($ 0x505) bit name description type 1 default register description: per-port software activated reset of the mac core. 0x00000000 31:10 reserved reserved r 0x00000 9 mac soft reset port 9 port 9 0 = reset inactive 1 = reset active r/w 0 8 mac soft reset port 8 port 8 0 = reset inactive 1 = reset active r/w 0 7 mac soft reset port 7 port 7 0 = reset inactive 1 = reset active r/w 0 6 mac soft reset port 6 port 6 0 = reset inactive 1 = reset active r/w 0 5 mac soft reset port 5 port 5 0 = reset inactive 1 = reset active r/w 0 4 mac soft reset port 4 port 4 0 = reset inactive 1 = reset active r/w 0 3 mac soft reset port 3 port 3 0 = reset inactive 1 = reset active r/w 0 2 mac soft reset port 2 port 2 0 = reset inactive 1 = reset active r/w 0 1 mac soft reset port 1 port 1 0 = reset inactive 1 = reset active r/w 0 0 mac soft reset port 0 port 0 0 = reset inactive 1 = reset active r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write table 83. cpu interface ($ 0x508) bit name description type 1 default register description: cpu interface endian select. this register allows the user to select the endian of the cpu interface to allow various different cpus to be connected to the ixf1110. 0x00000000 31:1 reserved reserved r 0x00000000 0endian 0 = little endian 1 = big endian r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 151 document number: 250210 revision number: 008 revision date: august 10, 2004 table 84. led control ($ 0x509) bit name description type 1 default register description: globally selects and enables the led mode. 0x00000000 31-2 reserved reserved r 0x00000000 1led enable 0 = disable leds 1 = enable leds r/w 0 0 led_sel_mode 0 = enable led mode 0 for use with sgs thompson m5450 led driver (default) 1 = led mode 1 for use with standard octal shift register r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write table 85. led flash rate ($ 0x50a) bit name description type 1 default register description: globally selects and enables the flash rate. 0x00000000 31:3 reserved reserved r 0x00000000 2:0 led flash rate 000 = 100 ms flash rate 001 = 200 ms flash rate 010 = 300 ms flash rate 011 = 400 ms flash rate 100 = 500 ms flash rate 101 = reserved 110 = reserved 111 = r eserved r/w 000 1. r = read only; cor = clear on read; w = write; r/w = read/write table 86. led fault disable ($ 0x50b) (sheet 1 of 2) bit name description type 1 default register description: per-port fault disable: disables the led flashing for local or remote faults 0x00000000 31:10 reserved reserved r 0x000000 9 led fault disable port 9 port 9 0 = fault enabled 1 = fault disabled r/w 0 8 led fault disable port 8 port 8 0 = fault enabled 1 = fault disabled r/w 0 7 led fault disable port 7 port 7 0 = fault enabled 1 = fault disabled r/w 0 6 led fault disable port 6 port 6 0 = fault enabled 1 = fault disabled r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 152 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5 led fault disable port 5 port 5 0 = fault enabled 1 = fault disabled r/w 0 4 led fault disable port 4 port 4 0 = fault enabled 1 = fault disabled r/w 0 3 led fault disable port 3 port 3 0 = fault enabled 1 = fault disabled r/w 0 2 led fault disable port 2 port 2 0 = fault enabled 1 = fault disabled r/w 0 1 led fault disable port 1 port 1 0 = fault enabled 1 = fault disabled r/w 0 0 led fault disable port 0 port 0 0 = fault enabled 1 = fault disabled r/w 0 table 87. jtag id revision ($ 0x50c) bit name description type default register description: the value of this register follows the same scheme as the device identification register found in the ieee 1149.1 specification. the upper 4 bits correspond to silicon stepping. the next 16 bits store a part id number. the next 11 bits contain a jedec manufacturer id. bit zero = 1 if the chip is the first in a stack. the encoding scheme used for the product id field is implementation dependent. 0x40456013 31:28 version 2 version 2 r0100 27:12 part id part id r 0000010001010110 11:8 jedec cont. jedec cont. r 0000 7:1 jedec id jedec id r 0001001 0 reserved reserved r 1 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. see the ixf1110 specification upate for the latest version. table 86. led fault disable ($ 0x50b) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 153 document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.5 global rx block register overview table 88 through table 93 on page 160 provide an overview of the rx block registers, which include the rx fifo high and low watermarks. table 88. rx fifo high watermark ports 0 to 9 ($ 0x580 - 0x589) (sheet 1 of 2) name 2 description address type 1 default rx fifo high watermark port 0 high watermark for rx fifo port 0. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x580 r/w 0x00000740 rx fifo high watermark port 1 high watermark for rx fifo port 1. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x581 r/w 0x00000740 rx fifo high watermark port 2 high watermark for rx fifo port 2. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x582 r/w 0x00000740 rx fifo high watermark port 3 high watermark for rx fifo port 3. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x583 r/w 0x00000740 rx fifo high watermark port 4 high watermark for rx fifo port 4. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x584 r/w 0x00000740 rx fifo high watermark port 5 high watermark for rx fifo port 5. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x585 r/w 0x00000740 rx fifo high watermark port 6 high watermark for rx fifo port 6. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x586 r/w 0x00000740 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all rx fifo high watermark registers, the following bit definitions apply to all ports (0:9): bits 31:15 - reserved and r. bits 14:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 154 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 rx fifo high watermark port 7 high watermark for rx fifo port 7. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x587 r/w 0x00000740 rx fifo high watermark port 8 high watermark for rx fifo port 8. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac 0x588 r/w 0x00000740 rx fifo high watermark port 9 high watermark for rx fifo port 9. the default value is 1856 bytes. when the amount of data stored in the fifo exceeds this value, a flow control command is sent to the corresponding tx mac. 0x589 r/w 0x00000740 table 89. rx fifo low watermark ports 0 to 9 ($ 0x58a - 0x593) (sheet 1 of 2) name 2 description address type 1 default rx fifo low watermark port 0 low watermark for rx fifo port 0. the default value is 1840 bytes. when the port is in flow control, and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58a r/w 0x00000730 rx fifo low watermark port 1 low watermark for rx fifo port 1. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58b r/w 0x00000730 rx fifo low watermark port 2 low watermark for rx fifo port 2. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58c r/w 0x00000730 rx fifo low watermark port 3 low watermark for rx fifo port 3. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58d r/w 0x00000730 rx fifo low watermark port 4 low watermark for rx fifo port 4. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58e r/w 0x00000730 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all rx fifo low watermark registers, the following bit definitions apply to all ports (0:9): bits 31:15 - reserved and r. bits 14:0 - described above. table 88. rx fifo high watermark ports 0 to 9 ($ 0x580 - 0x589) (sheet 2 of 2) name 2 description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all rx fifo high watermark registers, the following bit definitions apply to all ports (0:9): bits 31:15 - reserved and r. bits 14:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 155 document number: 250210 revision number: 008 revision date: august 10, 2004 rx fifo low watermark port 5 low watermark for rx fifo port 5. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x58f r/w 0x00000730 rx fifo low watermark port 6 low watermark for rx fifo port 6. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x590 r/w 0x00000730 rx fifo low watermark port 7 low watermark for rx fifo port 7. the default value is 1840 bytes.when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x591 r/w 0x00000730 rx fifo low watermark port 8 low watermark for rx fifo port 8. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x592 r/w 0x00000730 rx fifo low watermark port 9 low watermark for rx fifo port 9. the default value is 1840 bytes. when the port is in flow control and the amount of data stored in the fifo goes below this value, the flow control command is terminated in the corresponding tx mac. 0x593 r/w 0x00000730 table 89. rx fifo low watermark ports 0 to 9 ($ 0x58a - 0x593) (sheet 2 of 2) name 2 description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all rx fifo low watermark registers, the following bit definitions apply to all ports (0:9): bits 31:15 - reserved and r. bits 14:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 156 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 90. rx fifo number of frames removed ports 0 to 9 ($ 0x594 - 0x59d) (sheet 1 of 2) name 2 description address type 1 default rx fifo number of frames removed on port 0 this register counts all frames removed from the rx fifo for port 0 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x594 cor 0x00000000 rx fifo number of frames removed on port 1 this register counts all frames removed from the rx fifo for port 1 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x595 cor 0x00000000 rx fifo number of frames removed on port 2 this register counts all frames removed from the rx fifo for port 2 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x596 cor 0x00000000 rx fifo number of frames removed on port 3 this register counts all frames removed from the rx fifo for port 3 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x597 cor 0x00000000 rx fifo number of frames removed on port 4 this register counts all frames removed from the rx fifo for port 4 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x598 cor 0x00000000 1. r = read only; cor = clear on read; w = write; r/w = read/write. 2. for all number of frames removed registers, the following bit definitions apply to all ports (0:9): bits 31:22 - reserved and r. bits 21:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 157 document number: 250210 revision number: 008 revision date: august 10, 2004 rx fifo number of frames removed on port 5 this register counts all frames removed from the rx fifo for port 5 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x599 cor 0x00000000 rx fifo number of frames removed on port 6 this register counts all frames removed from the rx fifo for port 6 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x59a cor 0x00000000 rx fifo number of frames removed on port 7 this register counts all frames removed from the rx fifo for port 7 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x59b cor 0x00000000 rx fifo number of frames removed on port 8 this register counts all frames removed from the rx fifo for port 8 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x59c cor 0x00000000 rx fifo number of frames removed on port 9 this register counts all frames removed from the rx fifo for port 9 by meeting one of the following conditions: the rx fifo on this port becomes full frames are removed in conjunction with the rx fifo errored frame drop enable register ( table 92 on page 159 ) frames are greater than the maxframesize ( table 68 on page 134 ) 0x59d cor 0x00000000 table 90. rx fifo number of frames removed ports 0 to 9 ($ 0x594 - 0x59d) (sheet 2 of 2) name 2 description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write. 2. for all number of frames removed registers, the following bit definitions apply to all ports (0:9): bits 31:22 - reserved and r. bits 21:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 158 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 table 91. rx fifo port reset ($ 0x59e) bit name description type 1 default register description: the soft reset register for each port in the rx block. port id = bit position in the register. to make the reset active, the bit must be set high. for example, reset of port 4 implies register value = 0001.0000. setting the bit to 0 de-asserts the reset. 0x00000000 31:10 reserved reserved r 0x000000 9 rxfifoport 9 reset port 9 0 = de-assert reset 1 = reset r/w 0 8 rxfifoport 8 reset port 8 0 = de-assert reset 1 = reset r/w 0 7 rxfifoport 7 reset port 7 0 = de-assert reset 1 = reset r/w 0 6 rxfifoport 6 reset port 6 0 = de-assert reset 1 = reset r/w 0 5 rxfifoport 5 reset port 5 0 = de-assert reset 1 = reset r/w 0 4 rxfifoport 4 reset port 4 0 = de-assert reset 1 = reset r/w 0 3 rxfifoport 3 reset port 3 0 = de-assert reset 1 = reset r/w 0 2 rxfifoport 2 reset port 2 0 = de-assert reset 1 = reset r/w 0 1 rxfifoport 1 reset port 1 0 = de-assert reset 1 = reset r/w 0 0 rxfifoport 0 reset port 0 0 = de-assert reset 1 = reset r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 159 document number: 250210 revision number: 008 revision date: august 10, 2004 table 92. rx fifo errored frame drop enable ($ 0x59f) (sheet 1 of 2) bit name description type 1 default register description: this register is used in conjunction with the rx packet filter control register bits to select whether errored or filtered frames are to be dropped. 0x00000000 31:10 reserved reserved r 0x000000 9 rx fifo errored frame drop enable port 9 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 9: 0 = do not drop frames 1 = drop frames r/w 0 8 rx fifo errored frame drop enable port 8 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 8: 0 = do not drop frames 1 = drop frames r/w 0 7 rx fifo errored frame drop enable port 7 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 7: 0 = do not drop frames 1 = drop frames r/w 0 6 rx fifo errored frame drop enable port 6 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 6: 0 = do not drop frames 1 = drop frames r/w 0 5 rx fifo errored frame drop enable port 5 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 5: 0 = do not drop frames 1 = drop frames r/w 0 4 rx fifo errored frame drop enable port 4 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 4: 0 = do not drop frames 1 = drop frames r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 160 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 3 rx fifo errored frame drop enable port 3 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 3: 0 = do not drop frames 1 = drop frames r/w 0 2 rx fifo errored frame drop enable port 2 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 2: 0 = do not drop frames 1 = drop frames r/w 0 1 rx fifo errored frame drop enable port 1 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 1: 0 = do not drop frames 1 = drop frames r/w 0 0 rx fifo errored frame drop enable port 0 these bits are used in conjunction with the ?rx packet filter control ($ port_index + 0x19)? bits, allowing the user to select whether errored or filtered frames are to be dropped or not. port 0: 0 = do not drop frames 1 = drop frames r/w 0 table 93. rx fifo overflow event ($ 0x5a0) (sheet 1 of 2) bit name description type 1 default register description: this register provides a status if a fifo-full situation has occurred (for example, a fifo overflow). the bit position equals the port number. this register is cleared on read. 0x00000000 31:10 reserved reserved r 0x000000 9 rx fifo overflow event port 9 port 9 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 8 rx fifo overflow event port 8 port 8 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 7 rx fifo overflow event port 7 port 7 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 1. r = read only; cor = clear on read; w = write; r/w = read/write table 92. rx fifo errored frame drop enable ($ 0x59f) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 161 document number: 250210 revision number: 008 revision date: august 10, 2004 6 rx fifo overflow event port 6 port 6 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 5 rx fifo overflow event port 5 port 5 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 4 rx fifo overflow event port 4 port 4 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 3 rx fifo overflow event port 3 port 3 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 2 rx fifo overflow event port 2 port 2 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 1 rx fifo overflow event port 1 port 1 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 0 rx fifo overflow event port 0 port 0 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 table 93. rx fifo overflow event ($ 0x5a0) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 162 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.6 tx block register overview table 94 through table 100 on page 170 provide an overview of the tx block registers, which include the tx fifo high and low watermark. table 94. tx fifo high watermark ports 0 to 9 ($ 0x600 - 0x609) (sheet 1 of 2) name 2 description address type 1 default tx fifo high watermark port 0 high watermark for tx fifo port 0. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x600 r/w 0x00000630 tx fifo high watermark port 1 high watermark for tx fifo port 1. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x601 r/w 0x00000630 tx fifo high watermark port 2 high watermark for tx fifo port 2. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x602 r/w 0x00000630 tx fifo high watermark port 3 high watermark for tx fifo port 3. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x603 r/w 0x00000630 tx fifo high watermark port 4 high watermark for tx fifo port 4. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x604 r/w 0x00000630 tx fifo high watermark port 5 high watermark for tx fifo port 5. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x605 r/w 0x00000630 tx fifo high watermark port 6 high watermark for tx fifo port 6. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x606 r/w 0x00000630 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all tx fifo high watermark registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and r. bits 12:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 163 document number: 250210 revision number: 008 revision date: august 10, 2004 tx fifo high watermark port 7 high watermark for tx fifo port 7. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x607 r/w 0x00000630 tx fifo high watermark port 8 high watermark for tx fifo port 8. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x608 r/w 0x00000630 tx fifo high watermark port 9 high watermark for tx fifo port 9. the default value is 1584 bytes. when the amount of data stored in the fifo exceeds this value, the tx fifo indicates ?satisfied.? this implies further up in the system that no more data must be sent to this port. 0x609 r/w 0x00000630 table 95. tx fifo low watermark ports 0 to 9 ($ 0x60a - 0x613) (sheet 1 of 2) name 2 description address type 1 default tx fifo low watermark port 0 low watermark for tx fifo port 0. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60a r/w 0x000001d0 tx fifo low watermark port 1 low watermark for tx fifo port 1. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60b r/w 0x000001d0 tx fifo low watermark port 2 low watermark for tx fifo port 2. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60c r/w 0x000001d0 tx fifo low watermark port 3 low watermark for tx fifo port 3. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60d r/w 0x000001d0 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all tx fifo low watermark registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and r. bits 12:0 - described above. table 94. tx fifo high watermark ports 0 to 9 ($ 0x600 - 0x609) (sheet 2 of 2) name 2 description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all tx fifo high watermark registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and r. bits 12:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller 164 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 tx fifo low watermark port 4 low watermark for tx fifo port 4. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60e r/w 0x000001d0 tx fifo low watermark port 5 low watermark for tx fifo port 5. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60f r/w 0x000001d0 tx fifo low watermark port 6 low watermark for tx fifo port 6. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x610 r/w 0x000001d0 tx fifo low watermark port 7 low watermark for tx fifo port 7. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x611 r/w 0x000001d0 tx fifo low watermark port 8 low watermark for tx fifo port 8. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x612 r/w 0x000001d0 tx fifo low watermark port 9 low watermark for tx fifo port 9. the default value is 464 bytes. when the amount of data falls below this value, the tx fifo status indicates ?starving?. this implies further up in the system that more data must be sent to this port to prevent an underrun. 0x613 r/w 0x000001d0 table 95. tx fifo low watermark ports 0 to 9 ($ 0x60a - 0x613) (sheet 2 of 2) name 2 description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all tx fifo low watermark registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and r. bits 12:0 - described above.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 165 document number: 250210 revision number: 008 revision date: august 10, 2004 table 96. tx fifo mac transfer threshold ports 0 to 9 ($ 0x614 - 0x61d) (sheet 1 of 3) name 2 description 3 address type 1 default tx fifo mac transfer threshold port 0 sets the value at which the fifo begins to transfer data to the mac. the bottom 3 bits of this register are ignored, and the threshold is set in increments of 8-byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x614 r/w 0x00000100 tx fifo mac transfer threshold port 1 sets the value at which the fifo begins to transfer data to the mac. the bottom 3 bits of this register are ignored, and the threshold is set in increments of 8-byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x615 r/w 0x00000100 tx fifo mac transfer threshold port 2 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x616 r/w 0x00000100 tx fifo mac transfer threshold port 3 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x617 r/w 0x00000100 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all mac transfer threshold registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and r. bits 12:0 - described above. 3. for proper operation of the ixf1110, the mac transfer threshold must be set to greater than the maxburst1 on the spi4-2.
intel ? ixf1110 10-port gigabit ethernet media access controller 166 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 tx fifo mac transfer threshold port 4 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x618 r/w 0x00000100 tx fifo mac transfer threshold port 5 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x619 r/w 0x00000100 tx fifo mac transfer threshold port 6 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x61a r/w 0x00000100 table 96. tx fifo mac transfer threshold ports 0 to 9 ($ 0x614 - 0x61d) (sheet 2 of 3) name 2 description 3 address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all mac transfer threshold registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and r. bits 12:0 - described above. 3. for proper operation of the ixf1110, the mac transfer threshold must be set to greater than the maxburst1 on the spi4-2.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 167 document number: 250210 revision number: 008 revision date: august 10, 2004 tx fifo mac transfer threshold port 7 sets the value at which the fifo begins to transfer data to mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x61b r/w 0x00000100 tx fifo mac transfer threshold port 8 sets the value at which the fifo begins to transfer data to the mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x61c r/w 0x00000100 tx fifo mac transfer threshold port 9 sets the value at which the fifo begins to transfer data to the mac. the bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. if this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the fifo only are allowed. transfer begins when either the count value in this register is exceeded or an end-of-frame is received. 0x61d r/w 0x00000100 table 97. tx fifo overflow event ($ 0x61e) (sheet 1 of 2) bit name description type 1 default register description: this register provides status that a fifo- full situation has occurred (for example, a fifo overflow). the bit position equals the port number. this register is cleared on read. 0x00000000 31:10 reserved reserved r 0x000000 9 tx fifo overflow event port 9 port 9 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 8 tx fifo overflow event port 8 port 8 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 1. r = read only; cor = clear on read; w = write; r/w = read/write table 96. tx fifo mac transfer threshold ports 0 to 9 ($ 0x614 - 0x61d) (sheet 3 of 3) name 2 description 3 address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. for all mac transfer threshold registers, the following bit definitions apply to all ports (0:9): bits 31:13 - reserved and r. bits 12:0 - described above. 3. for proper operation of the ixf1110, the mac transfer threshold must be set to greater than the maxburst1 on the spi4-2.
intel ? ixf1110 10-port gigabit ethernet media access controller 168 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 7 tx fifo overflow event port 7 port 7 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 6 tx fifo overflow event port 6 port 6 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 5 tx fifo overflow event port 5 port 5 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 4 tx fifo overflow event port 4 port 4 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 3 tx fifo overflow event port 3 port 3 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 2 tx fifo overflow event port 2 port 2 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 1 tx fifo overflow event port 1 port 1 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 0 tx fifo overflow event port 0 port 0 0 = fifo overflow event did not occur 1 = fifo overflow event occurred cor 0 table 98. tx fifo drain ($0x620) (sheet 1 of 2) bit name description type 1 default register description: this register enables the tx fifo drain mode for the selected port by holding the tx fifo for that port in reset. all data stored in the tx fifo is lost when this bit is set to 1. when this bit is set to 1, the tx fifo status for the selected port is starving. 0x00000000 31:10 reserved reserved r 0x000000 9 tx fifo drain port 9 port 9 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 8 tx fifo drain port 8 port 8 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 7 tx fifo drain port 7 port 7 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 6 tx fifo drain port 6 port 6 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 1. r = read only; cor = clear on read; w = write; r/w = read/write table 97. tx fifo overflow event ($ 0x61e) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 169 document number: 250210 revision number: 008 revision date: august 10, 2004 5 tx fifo drain port 5 port 5 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 4 tx fifo drain port 4 port 4 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 3 tx fifo drain port 3 port 3 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 2 tx fifo drain port 2 port 2 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 1 tx fifo drain port 1 port 1 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 0 tx fifo drain port 0 port 0 0 = disable tx fifo drain mode 1 = enable tx fifo drain mode r/w 0 table 99. tx fifo info out-of-sequence ($ 0x621) (sheet 1 of 2) bit name description type 1 default register description: this register signals when out-of-sequence data is detected in the tx fifo. events such as sop followed by another sop cause this bit to be set and remain so until read. this register is cleared on read. 0x00000000 31:10 reserved reserved r 0x000000 9 tx fifo info out-of- sequence port 9 port 9 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 8 tx fifo info out-of- sequence port 8 port 8 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 7 tx fifo info out-of- sequence port 7 port 7 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 6 tx fifo info out-of- sequence port 6 port 6 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 1. r = read only; cor = clear on read; w = write; r/w = read/write table 98. tx fifo drain ($0x620) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 170 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 5 tx fifo info out-of- sequence port 5 port 5 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 4 tx fifo info out-of- sequence port 4 port 4 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 3 tx fifo info out-of- sequence port 3 port 3 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 2 tx fifo info out-of- sequence port 2 port 2 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 1 tx fifo info out-of- sequence port 1 port 1 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 0 tx fifo info out-of- sequence port 0 port 0 0 = fifo out-of-sequence event did not occur 1 = fifo out-of-sequence event occurred cor 0 table 100. tx fifo number of frames removed ports 0-9 ($ 0x622 - 0x62b) (sheet 1 of 2) name description address type 1 default tx fifo number of frames removed on port 0 this register counts the number of frames removed on port 0 due to a tx fifo overflow. 0x622 cor 0x00000000 tx fifo number of frames removed on port 1 this register counts the number of frames removed on port 1 due to a tx fifo overflow. 0x623 cor 0x00000000 tx fifo number of frames removed on port 2 this register counts the number of frames removed on port 2 due to a tx fifo overflow. 0x624 cor 0x00000000 tx fifo number of frames removed on port 3 this register counts the number of frames removed on port 3 due to a tx fifo overflow. 0x625 cor 0x00000000 tx fifo number of frames removed on port 4 this register counts the number of frames removed on port 4 due to a tx fifo overflow. 0x626 cor 0x00000000 tx fifo number of frames removed on port 5 this register counts the number of frames removed on port 5 due to a tx fifo overflow. 0x627 cor 0x00000000 1. r = read only; cor = clear on read; w = write; r/w = read/write table 99. tx fifo info out-of-sequence ($ 0x621) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 171 document number: 250210 revision number: 008 revision date: august 10, 2004 tx fifo number of frames removed on port 6 this register counts the number of frames removed on port 6 due to a tx fifo overflow. 0x628 cor 0x00000000 tx fifo number of frames removed on port 7 this register counts the number of frames removed on port 7 due to a tx fifo overflow. 0x629 cor 0x00000000 tx fifo number of frames removed on port 8 this register counts the number of frames removed on port 8 due to a tx fifo overflow 0x62a cor 0x00000000 tx fifo number of frames removed on port 9 this register counts the number of frames removed on port 9 due to a tx fifo overflow. 0x62b cor 0x00000000 table 100. tx fifo number of frames removed ports 0-9 ($ 0x622 - 0x62b) (sheet 2 of 2) name description address type 1 default 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 172 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.7 spi4-2 block register overview table 101 through table 104 on page 174 provide an overview of the spi4-2 block registers. table 101. spi4-2 rx burst size ($ 0x700) bit name description type 1 default register description: spi4-2 rx interface start-up parameters for burst size. 0x00060002 31 idles 0 = zero idle insertion between transfer bursts 1 = inserts four idle control words between each burst. (this occurs not only on an eop, but also at the end of every maxburst1 or maxburst2. r/w 0x0 30:25 reserved reserved r 0x00 24:16 maxburst1 maximum number of 16-byte blocks that the fifo in the receive path, external to the ixf1110, can accept when the fifo status channel indicates starving. note: do not program these bits below 0x2 (32 byte burst). r/w 0x006 15:9 reserved reserved r 0x00 8:0 maxburst2 maximum number of 16-byte blocks that the fifo in the receive path, external to the ixf1110, can accept when the fifo status channel indicates hungry. note: do not program these bits below 0x2 (32 byte burst). r/w 0x002 1. r = read only; cor = clear on read; w = write; r/w = read/write table 102. spi4-2 rx training ($ 0x701) bit name description type 1 default register description: spi4-2 rx interface start-up parameters for training sequences 0x00000000 31:24 reserved reserved r 0x00 23:16 rep_t number of repetitions of the data training sequence that must be scheduled every data_max_t cycles r/w 0x00 15:0 data_max_t 2 maximum interval (in number of cycles) between scheduling of training sequences on receive data path interface an all zero value disables periodic training sequences. r/w 0x0000 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. the value of data_max_t is the most significant 16 bits of a 24-bit counter value. the least significant 8 bits are always 0x00. this allows for a much larger dat_max_t time-out period and provides a more than adequate granularity of selection.
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 173 document number: 250210 revision number: 008 revision date: august 10, 2004 table 103. spi4-2 rx calendar ($ 0x702) bit name description type 1 default value register description: spi4-2 rx interface start-up parameters for fifo status calendar operation. 0x00010300 31:30 rx train test modes 00 = normal mode 01 = do not enter training based on a repeating ?11? pattern on rstat[1:0] 1x = train continuously r/w 0x0 29 rsclk_invert 0 = the fifo status is captured on the rising edge of the rsclk as per the spi4-2 specification 1 = the fifo status is captured on the falling edge of rsclk note: for proper operation, set this bit to the desired setting before the rsclk is applied to the device. r/w 0 28 tsclk_invert 0 = the fifo status is launched on the rising edge of the tsclk as per the spi4-2 specification 1 = the fifo status is launched on the falling edge of tsclk r/w 0 27:21 reserved reserved r 0x000 20 dip2_error set based on an incorrect rx dip2 result. this bit is cleared upon a read cor 0x0 19:16 dip-2_thr defines how many consecutive correct dip- 2s are required to disable sending of training sequences on the rx spi4-2. r/w 0x1 15:14 reserved reserved r 00 13 rx spi4-2 sync 0 = rx spi4 in training (rdat = training) rx spi4 out of training (rdat = idles) r0 12 tx spi4 sync 0 = tx spi4-2 calendar is in constant framing the tx spi4-2 has received the valid training patterns on tdat and is now sending a 10 port calendar on tsat with valid fifo information r0 11:8 loss_of_sync loss-of-sync is a parameter specifying the number of consecutive framing calendar cycles required to indicate a loss of synchronization and restart training sequences. r/w 0x3 7:4 reserved reserved r 0x0 3:0 reserved write as 0, ignore on read. r/w 0x0 1. r = read only; cor = clear on read; w = write only; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 174 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.8 serdes register overview table 105 through table 107 on page 175 define the contents of the serdes register block at base location 0x780 which contain the control and status for the ten serdes interfaces on the ixf1110. table 104. spi4-2 tx synchronization ($ 0x703) bit name description type 1 default register description: spi4-2 synchronization dip-4 counters. 0x00000420 31:16 dip4_errors dip4_errors is the total number of dip4 errors detected since this register was last read. cor 0x0000 15:8 dip4_unlock 2 dip-4_unlock is a spi4-2 parameter specifying the number of incorrect dip4 fields to be detected to declare loss of synchronization and drive the tstat[1:0] bus with framing. r/w 0x04 7:0 dip4_lock number of consecutive correct dip4 results to achieve synchronization and end training r/w 0x20 1. r = read only; cor = clear on read; w = write; r/w = read/write 2. when periodic training is enabled, the actual count of dip4 errors required to lose synchronization is 1 less than the programmed value in this register. therefore, this value should always be programmed to be 1 more than the desired value and should never be programmed to either 0 or 1. table 105. serdes tx driver power level ports 0-6 ($ 0x784) bit name description type 1 default register description: allows selection of various programmable drive strengths on each of the serdes ports. note: refer to table 21, ?serdes driver tx power levels? on page 71 for valid serdes power levels. 0x00000000 31:28 reserved reserved r 0x0 27:25 drvpwr6[3:0] encoded input that sets power level for port 6 r/w 1101 24:21 drvpwr5[3:0] encoded input that sets power level for port 5 r/w 1101 20:16 drvpwr4[3:0] encoded input that sets power level for port 4 r/w 1101 15:12 drvpwr3[3:0] encoded input that sets power level for port 3 r/w 1101 11:8 drvpwr2[3:0] encoded input that sets power level for port 2 r/w 1101 7:4 drvpwr1[3:0] encoded input that sets power level for port 1 r/w 1101 3:0 drvpwr0[3:0] encoded input that sets power level for port 0 r/w 1101 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 175 document number: 250210 revision number: 008 revision date: august 10, 2004 table 106. serdes tx driver power level ports 7-9 ($ 0x785) bit name description type 1 default register description: allows selection of various programmable drive strengths on each of the serdes ports. note: refer to table 21, ?serdes driver tx power levels? on page 71 for valid serdes power levels. 0x00000000 31:12 reserved reserved r 0x00000 11:8 drvpwr9[3:0] encoded input that sets power level for port 9 r/w 1101 7:4 drvpwr8[3:0] encoded input that sets power level for port 8 r/w 1101 3:0 drvpwr7[3:0] encoded input that sets power level for port 7 r/w 1101 1. r = read only; cor = clear on read; w = write; r/w = read/write table 107. serdes tx and rx power-down ports 0-9 ($ 0x787) bit name description type 1 default register description: tx and rx power-down bits to allow per-port power-down of unused ports 0x00000000 31:20 reserved reserved r 0x000 19:10 tpwrdwn[9:0] tx power-down for ports 0-9 (1 = power-down) r/w 0000000000 9:0 rpwrdwn[9:0] rx power-down for ports 0-9 (1 = power-down) r/w 0000000000 1. r = read only; cor = clear on read; w = write; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 176 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 8.5.9 optical module interface block register overview table 108 through table 111 provide an overview of the optical module interface block registers. these registers provide a means to control and monitor the interface to the optical modules. table 108. optical module status ports 0-9 ($ 0x799) bit name description type 1 default register description: this register provides optical module status information. 0x00000000 31:30 reserved reserved r 00 29:20 rx_los_9:0 rx_los inputs for ports 0-9 r 0000000000 19:10 tx_fault_9:0 tx_fault inputs for ports 0-9 r 0000000000 9:0 mod_def_9:0 mod_def inputs for ports 0-9 r 0000000000 1. r = read only; cor = clear on read; w = write only; r/w = read/write table 109. optical module control ports 0-9 ($ 0x79a) bit name description type 1 default register description: this register provides access to optical module interrupt enables and sets the tx_disable outputs. 0x00000000 31:13 reserved reserved r 0000000000 000000000 12 rx_los_en enable for rx_los_int operation 0 = disabled 1 = enabled r/w 0 11 tx_fault_en enable for tx_fault_int operation 0 = disabled 1 = enabled r/w 0 10 mod_def_en enable for mod_def_int operation 0 = disabled 1 = enabled r/w 0 9:0 tx_disable_9:0 tx_disable outputs for ports 0-9 r/w 0000000000 1. r = read only; cor = clear on read; w = write only; r/w = read/write table 110. i 2 c control ports 0-9 ($ 0x79b) (sheet 1 of 2) bit name description type 1 default register description: this register controls i 2 c reads and writes. 0x00000000 31:29 reserved reserved r 000 28 port address error port address error is set to 1 when an access is requested to port address > 0x9. r0 27 wp_err write protect error is set to 1 when a write access is requested to device id = 0xa and register address [10:8] = 0. this address combination is used solely for the read only optical module. r0 1. r = read only; cor = clear on read; w = write only; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 177 document number: 250210 revision number: 008 revision date: august 10, 2004 26 no_ack-err this bit is set to 1 when a optical module has failed to assert an acknowledge cycle. this signal should be used to validate the data being read. data is only valid if this bit is equal to zero. r0 25 i 2 cenable enables device wide i 2 c accesses (enabled = 1) r/w 0 24 i 2 c start i 2 c start = 1 will initiate the i 2 c cycle. this bit is clear on read. cor 0 23 reserved reserved r 0 22 write complete write complete is set to a 1 when the byte write cycle has completed. r0 21 reserved reserved r 0 20 read valid read valid is set to a 1 when valid data is available in the dataread7:0 field. r0 19:16 port address select 3:0 ixf1110 port address to be accessed r/w 0x0 15 read/write 0 = write 1 = read r/w 1 14:11 device id most significant 4 bits of device id/address field. r/w 0xa 10:0 register address bits 10:8 define least significant 3 bits of device id/ address field. bits 7:0 define the register address. r/w 00000000000 table 111. i 2 c data ports 0-9 ($ 0x79c) bit name description type 1 default register description: this register provides i 2 c reads and writes. 0x00000000 31:24 reserved reserved r 0x00 23:16 write data write_data contains the data to be written during the i 2 c byte write cycle. r/w 0x00 15:8 reserved reserved r 0x00 7:0 read_data read_data contains the byte received during the last i 2 c read cycle. r0x00 1. r = read only; cor = clear on read; w = write only; r/w = read/write ta ble 110 . i 2 c control ports 0-9 ($ 0x79b) (sheet 2 of 2) bit name description type 1 default 1. r = read only; cor = clear on read; w = write only; r/w = read/write
intel ? ixf1110 10-port gigabit ethernet media access controller 178 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 9.0 package overview cbga packages are suited for applications requiring high i/o counts and high electrical performance. they are recommended for high-power applications, having high noise immunity requirements. 9.1 features flip chip die attach; surface mount second-level interconnect high electrical performance high i/o counts area array i/o options multiple power zone offering supports core and four additional voltages jedec-compliant package 9.2 ixf1110 package specifics the ixf1110 uses the following packaging (see figure 44, ?intel? ixf1110 mac 552-ceramic ball grid array (cbga) package specifications? on page 180 ): 576-ball bga package with 6 balls removed diagonally from each corner, for a total of 552 balls used measuring 25 mm x 25 mm ball pitch of 1.0 mm overall package dimensions of 25 mm x 25 mm
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 179 document number: 250210 revision number: 008 revision date: august 10, 2004 9.2.1 markings character font size 0.04 - 0.10? 0.06 - 0.10? 25.0 mm 9.67 x 9.6 mm 25.0 mm p in 1 mark aaa000aaa = intel product number 0.19 - 0.24? ? 0.07 - 0.12? r note: * "pin 1 " does mean a pin1 indicator, not an actual mark. country xx = intel silicon revision number, a0, a1, b0 ? diameter of trademark circles are 70 mils substrate pn = substrate material number (barely visible) jjjjjjjj = manufacturing lot number syww9001 = intel finished process order (fpo) numb er country = assy plant country of origin topside fields not to scale diameter of pin 1 mark is 70 mils, and is located opposite the top-side substrate ?pin 1? identifier. qq = quality level, p: proto type, pq: pre-production, ? ?: production (no marking) ++ ++ = rework indicator syww9001 back of the die (bare silicon) substrate pn
intel ? ixf1110 10-port gigabit ethernet media access controller 180 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 figure 44. intel ? ixf1110 mac 552-ceramic ball grid array (cbga) package specifications b0612-01 4.8 4.835 chip substrate 9.6 9.67 (25 0.2) (25 0.2) 47p6802 note: all dimensions are in mm. b0611-02 1 b 2 (25 0.2) (23) (25 0.2) (23) (23x) typ chip carrier a01 corner (23x) typ (0.91 max) (0.33 min) (reference) (0.91 max) (0.33 min) (575x) ( ? 0.8 0.05) (i/o pads) (reference) ? 0.20 da l s b s note: all dimensions are in mm. = ball = no ball
intel ? ixf1110 10-port gigabit ethernet media access controller datasheet 181 document number: 250210 revision number: 008 revision date: august 10, 2004 figure 45. intel ? ixf1110 mac cbga package side view diagram b0610-01 seating plane 0.15 c (4.237 max) (3.519 min) (3.327 max) (2.809 min) (2.47 max) (2.03 min) 0.81 0.1 (0.857 max) (0.779 min) chip c4 encapsulant fillet 45l4867 (552) solder ball note: all dimensions are in mm.
intel ? ixf1110 10-port gigabit ethernet media access controller 182 datasheet document number: 250210 revision number: 008 revision date: august 10, 2004 10.0 product ordering information table 112. intel ? ixf1110 mac product information number revision qualification mm number ship media hfixf1110cc b2 b2 s 860817 tray figure 46. intel ? ixf1110 mac ordering information - sample temperature range a c e = ambient (0 - 55 c) = commercial (0 - 70 c) = extended (-40 - +85 c) product revision xn = 2 alphanumeric characters build format e000 e001 = tray = tape and reel hf s b2 c c 1110 ixf e000 internal package designator l p n q h t b c e k = lqfp = plcc = dip = pqfp = qfp with heat spreader = tqfp = bga = cbga = tbga = hsbga (bga with heat slug) qualification q s = pre-production material = production material ixa product prefix lxt ixe ixf ixp = phy layer device = switching engine = formatting device (mac) = network processor intel package designator dj fa fl fw hb hd hf hg s gc n = lqfp = tqfp = pbga (<1.0 mm pitch) = pbga (1.27 mm pitch) = qfp with heat spreader = qfp with heat slug = cbga = soic = qfp = tbga = plcc xxxx = 3-5 digit alphanumeric product cod e b2578-01

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